Nec Corporation

Naoaki Sudo

Hiroyuki Takahashi

Kazuo Watanabe

Toshikatsu Jinbo

Toshio Takeshima

Hironori Nakamura

Koji Naganawa

Satoshi Katagiri

According to one embodiment, a latch-type sense amplifier can reduce noise at a signal input that may be generated by capacitive coupling of a sense amplifier latch enable signal. A latch-type sense amplifier may include a first transfer gate TG between a first input SA and a first latch node N and a second transfer gate TG between a second input SA and a second latch node N A first transfer gate may include complementary transistors NM and PM Transistor NM can receive a control signal /SE at a control gate while transistor PM can receive a complementary control signal SE at a control gate. Transistor NM may include a parasitic capacitance CON and transistor PM may include a parasitic capacitance COP that is essentially equivalent to CON. In such an arrangement, noise at first input SA generated by capacitive coupling of a control signal SE can be reduced and/or cancelled by noise generated by capacitive coupling of a complementary control signal /SE.

Sense amplifier circuit and semiconductor storage device

According to one embodiment, a latch-type sense amplifier can reduce noise at a signal input that may be generated by capacitive coupling of a sense amplifier latch enable signal. A latch-type sense amplifier may include a first transfer gate TG between a first input SA and a first latch node N and a second transfer gate TG between a second input SA and a second latch node N A first transfer gate may include complementary transistors NM and PM Transistor NM can receive a control signal /SE at a control gate while transistor PM can receive a complementary control signal SE at a control gate. Transistor NM may include a parasitic capacitance C N and transistor PM may include a parasitic capacitance C P that is essentially equivalent to C N. In such an arrangement, noise at first input SA generated by capacitive coupling of a control signal SE can be reduced and/or cancelled by noise generated by capacitive coupling of a complementary control signal /SE.

A nonvolatile semiconductor device is provided, which does not need excessive writing or verification operations, except for the originally required writing and verification operations. The data is arranged in the order from the lowest &ldquo;11&rdquo;, &ldquo;10&rdquo;, &ldquo;01&rdquo;, to the highest &ldquo;01&rdquo;. Four valued writing data are set in the latches and by data signals DL and DL and the latch is initialized to &ldquo;0&rdquo;. Writing is executed by three stages, and before writing at each stage, if the latch is &ldquo;0&rdquo;, the data is transferred to the latch Writing is only executed when any one latch is &ldquo;0&rdquo;, and the latch is changed to &ldquo;1&rdquo; after the verification is completed. First, writing is executed up to the threshold value of the data &ldquo;01&rdquo;, except the data &ldquo;11&rdquo; where the latch is &ldquo;0&rdquo;. Next, writing is executed for the data &ldquo;00&rdquo; and &ldquo;01&rdquo; up to the threshold value of the data &ldquo;00&rdquo;, where the latch is &ldquo;0&rdquo;. Finally, the data &ldquo;01&rdquo; where the latch is &ldquo;0&rdquo; is written up to the threshold value of &ldquo;01&rdquo;.

Nonvolatile semiconductor memory device

To provide a semiconductor storage apparatus capable of reducing a chip area, one main bit line is provided to a plurality of sub bit lines commonly connected with drains of memory cell transistors, the plurality of the bit lines are connected to ends on one side of switches at a first stage, control terminals of which are respectively inputted with column selecting signals and ends on other side of the switches are commonly connected and connected to the main bit line via a switch at a second stage, a control terminal of which is inputted with a column selecting signal, the sub bit lines are wired to a first wiring layer, the main bit line is wired to a second wiring layer and the second wiring layer is wired with power source lines, lines of voltage control signals in erasing or writing and high voltage power supply lines in regions among the main bit lines.

Semiconductor storage apparatus having main bit line and sub bit line

Boost circuit units are connected in parallel. A boost output voltage V,&prime; of a dummy boost circuit unit having the same configuration as the boost circuit units is detected by a voltage detection circuit. The voltage detection circuit outputs a signal TBST,which becomes &ldquo;high&rdquo; when V,&prime; is lower than V,and &ldquo;low&rdquo; when V,&prime; is equal to or higher than V,. The TBST,signal is input to a NAND circuit. When a &ldquo;high&rdquo; signal is input to the NAND circuit, an input voltage ATDBST,is input to the boost circuit unit as well via the NAND circuit and the two boost circuit units perform boost operation. Thus, a boost circuit can suppress the dispersion of the boost voltage caused by the dispersion of the process condition and the variation of the external temperature besides the variation of the power supply voltage Vcc.

Boost circuit

According to one embodiment, a latch-type sense amplifier can reduce noise at a signal input that may be generated by capacitive coupling of a sense amplifier latch enable signal. A latch-type sense amplifier may include a first transfer gate TG,between a first input SA,and a first latch node N,and a second transfer gate TG,between a second input SA,and a second latch node N,A first transfer gate may include complementary transistors NM,and PM,Transistor NM,can receive a control signal /SE at a control gate while transistor PM,can receive a complementary control signal SE at a control gate. Transistor NM,may include a parasitic capacitance C,N and transistor PM,may include a parasitic capacitance C,P that is essentially equivalent to C,N. In such an arrangement, noise at first input SA,generated by capacitive coupling of a control signal SE can be reduced and/or cancelled by noise generated by capacitive coupling of a complementary control signal /SE.

A reference voltage generating circuit with MOS transistors having a floating gate is disclosed. The reference voltage generating circuit has first and second MOS transistors in which substantially the same current flows by means of a current mirror circuit. The differential voltage between the threshold voltages of the first and second MOS transistors is applied from the source of the first transistor as the reference voltage. The first and second transistors are of a construction that includes a floating gate, and the threshold voltage can be set to any value by means of the amount of charge injected to the floating gate.

Reference voltage generating circuit with MOS transistors having a floating gate

There is provided a word-line driving circuit has: two P-channel type transistors which are connected in a flip-flop configuration and one of which is connected between a first power supply and a word line; an N-channel transistor which is connected between a signal obtained by decoding a low-order address and a gate of the above-mentioned one P-channel type transistor and which has its gate connected with a signal obtained by decoding a high-order address; a first NN-channel type transistor which is connected between a word line and a second power supply and which has its gate connected with the signal obtained by decoding a low-order address; and a second NN-channel type transistor which is connected between a word line and the second power supply and which has its gate connected with the signal obtained by decoding a high-order address.

Word-line driving circuit and semiconductor memory device

A boosting circuit includes a plurality of boosting circuit units, a voltage detecting circuit and a boost control circuit. The plurality of boosting circuit units have their outputs connected together and respectively having voltage boosting functions. Each of the plurality of boosting circuit units generates a boosted voltage higher than a power supply voltage in response to a drive signal. The voltage detecting circuit detects whether or not the boosted voltage is higher than a predetermined voltage, to generate a voltage control signal when it is detected that the boosted voltage is higher than a predetermined voltage. The boost control circuit limits the voltage boosting functions of predetermined ones of the plurality of boosting circuit units in response to the voltage control signal.

Boosting circuit with boosted voltage limited

The object of the present invention is to reduce the dispersion of the threshold after writing while maintaining the high speed nature of a write system in a nonvolatile semiconductor memory such as a flash memory of channel hot electron write type. The feature of this invention is to provide a memory with a write current detection type write circuit and a sense amplifier for read, and to switch, for verification at the time of write, between verification by the write current type write circuit and verification of normal read mode which uses the sense amplifier for read. In other words, when a cell threshold of write level is designated as a first threshold and a specified threshold level lower than the first threshold is designated as a second threshold, write operation by the write current detection type write circuit is performed at the beginning of write mode, and stops the write operation when the current flowing between the drain and the source of the memory cell falls to below or equal to the reference current corresponding to the second threshold. Thereafter, the write operation is performed by repeating the write operation and verification operation using the sense amplifier until the cell threshold reaches the first threshold.

Nonvolatile semiconductor memory device including sense amplifier having

A plurality of diode-connected MOS transistors are arranged in cascade connection, and clocks are supplied to nodes between the MOS transistors. A node (N40) is connected to a first voltage source line (VCC) via a first switch (SW1), a node (N46) is connected to a second voltage source (GND) via a second switch (SW2), an intermediate node (N43) is connected to a third voltage source (VCC) via a third switch (SW3). The third switch is turned ON and the first and second switches are turned OFF to output the positive high voltage (VPP) from the node (N46) and also to output the negative high voltage (VBB) from the node (N40).

High voltage generating circuit able to generate positive high voltage

In order to provide a voltage booster circuit to be controlled for generating either of a positive high voltage and a negative high voltage for economizing chip size, a voltage booster circuit of the invention, having a charge transfer circuit wherein charges are transfered from a lowest node (N10) to a highest node (N15), comprises switching means (1 and 2) for selecting one of a positive high voltage output mode and a negative high voltage output mode. A positive high voltage (VPP) is output from the highest node (N15) by supplying a power supply voltage (VCC) to the lowest node (N10) in the positive high voltage output mode, and a negative high voltage (VBB) is output from the lowest node (N10) by grounding the highest node (N15) in the negative high voltage output mode.

Voltage booster circuit

In a nonvolatile semiconductor memory, in addition to a first voltage generating circuit for supplying various voltages to memory cell transistors in various operations, there is provided a second voltage generating circuit for supplying various voltages to a dummy cell in a reference voltage generating circuit in the various operations. The second voltage generating circuit is configured to supply a dummy cell writing voltage to the dummy cell, one time only when the erase operation for the memory cell transistors has been carried out. Accordingly, with a very simple construction, the progress of the deterioration of the dummy cell and the memory cell transistor can be made close to each other, so that the working life of the nonvolatile semiconductor memory can be lengthened.

Growing community of inventors

Tokyo, Japan

Naoaki Sudo