Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitisu Limited

Naoaki Naka

Junko Nakamoto

Junko Maeda

Shigeru Nishio

Yanyan Qiao

A semiconductor integrated circuit including: a data input circuit inputting a data input signal from outside and outputting the signal; a comparison value register memorizing an expectation value of the output signal varying in accordance with an input to the data input circuit; and a comparing circuit comparing a value in accordance with a switching number of the output signal of the data input circuit and the expectation value, is provided.

Semiconductor integrated circuit

An output circuit of the present invention includes a data output circuit and a clock output circuit. The output circuit includes a first D-type flip-flop and a selector for selectively outputting an output from the first D-type flip-flop or second data according to a selection signal. The clock output circuit includes a second D-type flip-flop, a third D-type flip-flop, and a dummy selector circuit. The dummy selector circuit is connected to the second and third D-type flip-flops and outputs a clock signal by using the same elements as those of the selector in order to realize the same delay time as that of the selector.

High precision data and clock output circuit

In the level converter circuit, when input signal is L level, a first NMOS transistor and a first PMOS transistor P are turned on by a first power supply potential, a second power supply potential is output to a first output terminal, a second NMOS transistor is turned on, and thereby, a reference potential VSS is output to a second output terminal. On the other hand, when the input signal is H level, a third NMOS transistor is turned on, the reference potential is output to the first output terminal, a fourth NMOS transistor and a second PMOS transistor are turned on, and thereby, the first power supply potential VDH is output to the second output terminal.

Level converter circuit

An amplification circuit of the present invention includes a first MOS transistor having a gate to which a first input terminal for inputting a positive logic input signal or a reference potential is connected and a drain to which a first load is connected, a second MOS transistor having a gate to which a second input terminal for inputting a negative logic input signal, which composes differential input signals with the positive logic signal, or the reference potential is connected and a drain to which an output terminal and a second load are connected, and pairing up with the first MOS transistor, and a current source to which sources of the first and second MOS transistors are connected, for supplying a constant current when the difference in voltage between the first and second input terminals is in a predetermined range, and varying the current to be supplied when the difference in voltage is beyond the predetermined range.

Amplification circuit with constant output voltage range

The invented test equipment, includes a circuit under test including a first terminating resistance connected to a first terminal; a first test circuit for outputting a high-speed test signal to said circuit under test via the second terminal; a tester connecting its third terminal to the second terminal of said first test circuit when said first test circuit outputs the high-speed test signal, or connecting a second test circuit for outputting a low-speed test signal to said circuit under test via its third terminal when said first test circuit does not output the high-speed test signal; and a determination circuit for evaluating the outputted signal of said circuit under test. A wiring between the first terminating resistance, the first terminal, the second terminal, the third terminal, and the second terminating resistance is joined in this serial order, when said tester connects the second terminating resistance to the third terminal.

Test equipment

A differential amplifier circuit comprising a pair of input MOS transistors, wherein inputs are supplied to the gates thereof, load circuits are connected to the drains thereof, and a current source is connected to the sources thereof, the current value of the current source is altered in line with variations in the characteristics of the input MOS transistors, thereby suppressing variations in the output level generated at the drain terminals of the input MOS transistors. In other words, unlike a conventional differential amplifier circuit, the current value of the current source is not kept to a uniform value, but rather is altered in accordance with the transistor characteristics generated by the manufacturing process.

Differential amplifier circuit and pull up-type differential driver

A pull-up circuit includes a pull-up transistor of a P-channel type having a drain coupled to a bus via a terminal, a source, a gate and a back gate, and a control circuit controlling the pull-up transistor so that no currents flow in a first current path formed from the drain to the back gate and a second path formed from the drain to the source.

Pull-up circuit and semiconductor device using the same

A power-supply circuit 121 generates a potential Vw which is approximately the higher of a power-supply potential VDD and a potential Vo at an output to set the potential Vw at an N-well of a pMOS pull-up transistor Qu equal to or higher than the potential at the source S and the drain D of the pMOS transistor Qu. The power-supply circuit 122 generates a potential Vs approximately equal to VDD--Vth when Vo&lt;VDD, and turns off when Vo&gt;VDD to prevent a current from flowing from the output OUT through the pMOS transistor Qu to the power-supply potential VDD, where Vth is the threshold voltage of the MOS transistors.

Growing community of inventors

Kawasaki, Japan

Naoaki Naka