Renesas Electronics Corporation

Renesas Electronics Coproration

Nao Nagata

Koji Tateno

Daisuke Kondo

Chang Liu

A semiconductor device includes first and second active cell regions and an inactive cell region between the first and second active cell regions, wherein each of the first and second active cell regions comprises: a trench gate; a first trench emitter; a first hole barrier layer of a first conductivity type formed between the trench gate and the first trench emitter; a base layer of a second conductivity type formed on upper portion of the first hole barrier layer; an emitter layer of the first conductivity type formed on upper portion of the base layer; a latch-up prevention layer of the second conductivity type formed on upper portion of the first hole barrier layer, wherein the inactive cell region comprises: a second trench emitter; a first floating layer of the second conductivity type formed between the trench gate of the first active cell region and the second trench emitter.

Semiconductor device

A semiconductor device includes a semiconductor substrate having first and second surfaces, an insulated gate bipolar transistor (IGBT) and a diode formed on the semiconductor substrate, wherein the diode comprises a drift layer of a first conductivity type formed so as to have a first region on the first surface of the semiconductor substrate, a first body layer of a second conductivity type formed so as to have a second region adjacent to the first region at an upper portion of the drift layer, a first floating layer of the second conductivity type formed so as to have a third region adjacent to the first region at an upper portion of the drift layer, a first trench electrode formed in a region adjacent to the first floating layer at an upper portion of the drift layer, and a first control gate formed on top of the first region.

A semiconductor device includes a semiconductor substrate, first and second trench electrodes formed on the semiconductor substrate, a floating layer of a first conductivity type formed around the first and second trench electrodes, a floating separation layer of a second conductivity type formed between the first and second trench electrodes and contacted with the floating layer of the first conductivity type and a floating layer control gate disposed on the floating separation layer of the second conductivity type.

A semiconductor device having an IE-type IGBT structure comprises a stripe-shaped trench gate and a stripe-shaped trench emitter arranged to face the trench gate formed in a semiconductor substrate. The semiconductor device further comprises an N-type emitter layer and a P-type base layer both surrounded by the trench gate and the trench emitter formed in the semiconductor substrate. The semiconductor device also comprises a P-type base contact layer arranged on one side of the trench emitter and formed in the semiconductor substrate. The p-type base contact layer, the emitter layer, and the trench emitter are commonly connected with an emitter electrode. The trench emitter is formed deeper than the trench gate in a thickness direction of the semiconductor substrate.

Semiconductor device having injection enhanced type insulated gate bipolar transistor with trench emitter and method of manufacturing the same

To enhance the performance of a semiconductor device. Gate electrodes extending in a Y direction and applied with a gate potential, and emitter regions and base regions both applied with an emitter potential are formed in an active cell area. The plural emitter regions are formed so as to be separated from each other in the Y direction by the base regions. A plurality of hole discharge cell areas having a ring-shaped gate electrode applied with an emitter potential are formed within an inactive cell area. The hole discharge cell areas are arranged to be separated from each other along the Y direction. Thus, an input capacitance of an IGBT is reduced, and a switching loss at turn on of the IGBT is improved.

Semiconductor device and manufacturing method therefor

A semiconductor device and a method of manufacturing a semiconductor device capable of suppressing breakdown due to current concentration while suppressing an increase in chip size are provided. According to one embodiment, a semiconductor device has a gate resistance on a main surface side of a semiconductor substrate, a first contact and a second contact connected to an upper surface of the gate resistance, and a carrier discharging portion that discharges the carrier formed in the semiconductor substrate below the gate resistance, the gate resistance having a first contacting portion to which a first contact is connected, a second contacting portion to which a second contact is connected, and a plurality of extending portions with one end connected to the first contacting portion and the other end connected to the second contacting portion. The gate resistance forms an opening between adjacent extending portions and the carrier discharge portion is formed in the opening.

Semiconductor device and method of manufacturing the same

A semiconductor device including an IE-type trench gate IGBT requires to be improved in IE effect to reduce on voltage. The semiconductor device includes a trench gate electrode or a trench emitter electrode between an active cell region and an inactive cell region. The trench gate electrode and the trench emitter electrode are provided across the inactive cell region.

A semiconductor device include a semiconductor substrate, a first trench electrode formed in the semiconductor substrate and having a first portion, a second trench electrode formed in the semiconductor substrate having a second portion facing the first portion, a floating layer of a first conductivity type formed around the first and second trench electrodes, a drift layer of a second conductivity type connected to the floating layer of the first conductivity type and formed between the first and second trench electrodes, an impurity layer of the first conductivity type connected to the drift layer of the second conductivity type and formed between the first and second trench electrodes, and a floating layer control gate having a portion located at least above the impurity layer of the first conductivity type.

Performance of a semiconductor device is improved. An active cell region has a first gate electrode that extends in a Y direction and receives a gate potential, and a second gate electrode that extends in the Y direction and receives an emitter potential. A hybrid cell region including a p-type base region and an n-type emitter region is disposed in the active cell region. An n-type isolation region adjacent to the hybrid cell region in the Y direction is formed in the active cell region excluding the hybrid cell region. Hence, even if the p-type base region or a p-type floating region is formed in the active cell region excluding the hybrid cell region, such a p-type region is isolated from the base region in the hybrid cell region by the isolation region.

Semiconductor device having an insulated gate bipolar transistor and method of manufacturing the same

An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a first trench gate electrode and second and third trench gate electrodes located on both sides of the first trench gate electrode interposed therebetween. In each of a semiconductor layer located between the first and second trench gate electrodes and the semiconductor layer located between the first and third trench gate electrodes, a plurality of p-type semiconductor regions are formed. The p-type semiconductor regions are arranged along the extending direction of the first trench gate electrode in plan view to be spaced apart from each other.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a first trench gate electrode and a second trench gate electrode which are electrically connected to a gate electrode, and a third trench gate electrode and a fourth trench gate electrode which are electrically connected to an emitter electrode. A plurality of ptype semiconductor regions are formed in a part of a semiconductor layer between the first trench gate electrode and the second trench gate electrode. The plurality of ptype semiconductor regions are arranged to be spaced apart from each other along an extending direction of the first trench gate electrode when seen in a plan view.

A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.

An improvement is achieved in the IE effect of a semiconductor device including an IGBT having an active cell region with an EGE structure. Each of a plurality of hybrid cell regions extending in a Y-axis direction has first, second, and third trench electrodes extending in the Y-axis direction, a p-type body region, and contact trenches provided between the first and second trench electrodes and between the first and third trench electrodes to extend in the Y-axis direction and reach middle points in the p-type body region. Each of the hybrid cell regions further has a plurality of n-type emitter regions formed in an upper surface of a semiconductor substrate located between the contact trenches and the first trench electrode to be shallower than the contact trenches and spaced apart at regular intervals in the Y-direction in plan view. The n-type emitter regions are arranged in a staggered configuration in plan view.

Growing community of inventors

Tokyo, Japan

Nao Nagata