International Business Machines Corporation

Nany H Kollesar

Shawn Kollesar

Leslie C Garcia

Huei Ling

A system to develop an integrated circuit includes a child placement module that places in a parent macro a child macro that contains therein a child logic circuit component. The parent macro has a first hierarchical level assigned thereto and the child macro has a lower second hierarchical level assigned thereto. The system further includes a timing analysis module and a component targeting module. The timing analysis module detects a timing fault in response to performing a first parent-level optimization process on the parent macro. The component targeting module extracts from the child macro a targeted logic circuit component and places the targeted logic circuit component in the parent macro. The timing analysis module performs a second parent-level optimization process on the parent macro that resolves the timing fault based on the placement of the targeted logic circuit component in the parent macro.

Multi-level hierarchical large block synthesis (hLBS) latch optimization

A floating point arithmetic unit that executes a single compound instruction that produces the result A+B.times.C with A, B and C being floating point numbers. Arithmetic on the exponents of A, B and C provide a normalized result of the multiplication before the addition takes place producing a normalized result of the compound instruction. The final normalized result is identical to a result that would be obtained by executing a separate instruction for the multiply, with normalized result, followed by an add instruction with a normalized result.

Growing community of inventors

Poughkeepsie, NY, United States of America

Nany H Kollesar