International Business Machines Corporation

Nanju Na

Nam Huu Pham

Lloyd Andre Walls

Bhyrav M Mutnury

Moises Cases

Daniel Mark Dreps

Jose A Hejase

Tae Hong Kim

Patrick Allen Buckland

Kaveh Naderi

James E Smith

Suzanne M Nolen

Michael D Hasse

Terence K Rodrigues

Jose A Hajase

Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator.

Noise modulation for on-chip noise measurement

Method for repairing a communication link failure. In certain embodiments, the method generally includes communicating with another apparatus using an initial number of channels of a plurality of channels of a communication link; selectively coupling a plurality of communication lanes with the plurality of channels of the communication link, wherein, during an initial state, a first lane of the plurality of lanes is coupled with a first channel of the plurality of channels, and wherein the plurality of channels comprises a spare channel; determining whether at least one channel of the plurality of channels is experiencing a failure; and controlling at least one of the multiplexers such that the failed channel is replaced by another channel of the plurality of channels by using the spare channel.

Dynamic link repair from lane failure with minimal link-down time while sparing fault channels

Computer program product and apparatus for repairing a communication link failure. In certain embodiments, the apparatus generally includes a controller configured to initialize the communication link for communication with another apparatus using an initial number of channels of a plurality of channels. The apparatus may also include a plurality of multiplexers configured to selectively couple a plurality of communication lanes with the plurality of channels of the communication link. In certain embodiments, during an initial state, a first lane of the plurality of lanes may be coupled with a first channel of the plurality of channels, and the plurality of channels may include a spare channel. The controller may determine whether at least one channel of the plurality of channels is experiencing a failure and control at least one of the multiplexers such that the failed channel is replaced by another channel of the plurality of channels by using the spare channel.

Dynamic link repair from lane failure with minimal link down-time while sparing fault channels

Mechanisms, in a data processing system comprising an input/output subsystem implementing an industry standard optical bus, for handling a failure of an optical channel in an optical bus are provided. The mechanisms detect, by failure detection logic of the input/output (I/O) subsystem, failure of an optical channel of the optical bus. The mechanisms send, by a controller of the I/O subsystem, a control signal to channel routing logic of the I/O subsystem to control a routing of data signals between active bus lanes of the data processing system and optical channels of the optical bus in response to detecting the failure of the optical channel. The mechanisms control, by the channel routing logic, routing of data signals between the active bus lanes and the optical channels so as to remove the failed optical channel from further use and use a spare optical channel instead of the failed optical channel.

Dynamic optical channel sparing in an industry standard input/output subsystem

A printed circuit board is disclosed. The printed circuit board includes a first signal transmission layer, a via and a second signal transmission layer. The via connects the first signal transmission layer to the second signal transmission layer. The via includes a first region made of a first dielectric material having a first dielectric constant, and a second region made of a second dielectric material having a second dielectric constant lower than the first dielectric constant. The via allows AC Component of an electromagnetic signal to be transmitted from the first signal transmission layer to the second signal transmission layer while blocking any DC component of the electromagnetic signal.

Printed circuit board having DC blocking dielectric waveguide vias

An improved electrical connector for connecting bus lines to a card such as a memory card or media card, including a multi-level connector comprising a latching device having a plurality of insertable latch positions that advantageously allows for selectively connecting or isolating an electrical path to an adjoining connector. The connectors of unpopulated DIMM slots are disconnected from the network along with the traces that would normally form a stub with associated undesirable signal reflections that would otherwise disturb the signal transmitted to the receiving end if not properly terminated. The contacts of the edge connector itself are used as a means to selectively connect or disconnect adjacent/downstream cards in a serially cascaded architecture. The burden of the stubs due to unpopulated card slots and the need to place one card at the far end of the network are thus eliminated.

Multi-level connector and use thereof that mitigates data signaling reflections

Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.

Minimizing plating stub reflections in a chip package using capacitance

Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations.

Mitigation of plating stub resonance by controlling surface roughness

Methods, apparatuses, and computer program products are disclosed for controlling plating stub reflections in a chip package. In one embodiment, a resonance optimizer determines performance characteristics of a bond wire that connects a chip to a substrate of a semiconductor chip mount. In this embodiment, the resonance optimizer selects, based on the performance characteristics of the bond wire, a line width for an open-ended plating stub that extends from a signal interconnect of the substrate to a periphery of the substrate, The resonance optimizer also generates a design of signal traces for the substrate, where the signal traces include the open-ended plating stub with the selected line width.

Controlling plating stub reflections in a chip package

Improving signal quality in a high-frequency chip package by resistively connecting an open-ended plating stub to ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A conductive first layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A resistor is used to resistively couple the plating stub to a ground layer.

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Essex Junction, VT, United States of America

Nanju Na