Chinese Academy of Sciences

Nanjian Wu

Jingjing Chen

Haiyong Wang

Jie Yang

Zhao Zhang

Cong Shi

Xiaodong Liu

Peng Feng

Qi Qin

Zhiqiang Guo

Liyuan Liu

Weiyang Liu

Wenfeng Lou

Xitian Long

A wireless radio-frequency transmission apparatus includes a phase frequency detector, a charge pump, a loop filter and a twin voltage-controlled oscillator. The twin voltage-controlled oscillator includes a first oscillator and a second oscillator. When the twin voltage-controlled oscillator is in a reception mode, the first and the second oscillators are coupled to each other to form a quadrature voltage-controlled oscillator, and the quadrature voltage-controlled oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop to generate quadrature carriers. When the twin voltage-controlled oscillator is in a transmission mode, the first oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop, and the second oscillator performs frequency modulation on transmitted data. The present disclosure can maintain a carrier frequency to be stable during high data rate transmission, and have a relatively short locking time of frequency hopping.

Wireless radio-frequency transmission apparatus

The present disclosure discloses a multi-standard performance reconfigurable I/Q orthogonal carrier generator. The generator may implement a continuously covered I/Q carrier output of 0.1-5 GHz and continuously covered differential signal outputs of 5-10 GHz and 1.5-3 GHz by means of reasonable frequency assignment; also, carrier signals under various frequencies with different loop bandwidths, different phase noises, different power consumption levels and different locking times can be generated by configuring a programmable charge pump (), a loop filter () parameter, a multi-path voltage-controlled oscillator () and a first multiplexer () corresponding thereto, a five-stage-division-by-two frequency division link () and a corresponding second multiplexer () and third multiplexer (), so as to implement generation of a multi-standard performance reconfigurable I/Q orthogonal carrier.

Multi-standard performance reconfigurable I/Q orthogonal carrier generator

The present disclosure provides an analog readout preprocessing circuit for a CMOS image sensor and a control method thereof. The analog readout preprocessing circuit comprises an extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion capacitor networkconfigured to achieve readout and analog-to-digital conversion of signals output from the CMOS image sensor; an operational amplifier configured to utilize 'virtual short' of two input terminals of the operational amplifier and the charge conservation principle, to achieve a function of extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion, where the extended count-type integration can effectively reduce a thermal noise and a flicker noise within the image sensor; a comparator configured to compare voltages at two terminals to achieve a function of quantization of signals; and a control signal generator configured to provide control signals.

Analog readout preprocessing circuit for CMOS image sensor and control method thereof

The present invention proposes a dynamically reconfigurable multi-level parallel single instruction multiple data array processing system which has a pixel level parallel image processing element array and a row-parallel array processor. The PE array mainly implements a linear operation which is adapted to be executed in parallel in the low and middle levels of image processing and the RP array implements an operation which is adapted to execute in row-parallel in the low and middle levels of image processing or more complex nonlinear operations. In particularly, such a system can be dynamically reconfigured as an SOM neural network at a low cost of area, and the neural network supports high level of image processing such as a high speed online neural network training and image feature recognition, and completely overcomes a defect that a high level of image processing can't be done by pixel-level parallel processing array in the existing programmable vision chips and parallel vision processors, and facilitates an intelligent and portable real time on-chip vision image system with a complete function at low device cost and low power consumption.

Dynamically reconstructable multistage parallel single instruction multiple data array processing system

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Beijing, China

Nanjian Wu