Industrial Technology Research Institute

Taiwan Semiconductor Manufacturing Comp. Ltd.

Nang-Ping Tu

Mingo Liu

Fu-Lung Hsueh

Chia-Yuan Chang

Yung-Yuan Ho

I-Fey Wang

Jian-Yau Yih

Ming-Daw Chen

Chien-Cheng Tu

Shaw-Jia Hor

Jung-Dar Ho

Yong-Nian Rau

Fu-Long Hsueh

A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Two-stage DAC architecture for LCD source driver utilizing one-bit serial charge redistribution DAC

An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type digital-to-analog converter (DAC) and at least one second channel type DAC. The integrated circuit further includes a plurality of sample and hold (S/H) circuits, each of the plurality of S/H circuits being coupled with a single DAC of the DAC circuit. A number of the at least one first channel type DAC is different than a number of the at least one second channel type DAC.

Integrated circuits, liquid crystal display (LCD) drivers, and systems

A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a two-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

DAC architecture for LCD source driver

A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Two-stage DAC achitecture for LCD source driver utilizing one-bit pipe DAC

An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel.

An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with one of the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel.

A method of testing a reflection-type LCD projector is disclosed. The present invention provides a method of testing the digital-circuit portion of the data drivers of the silicon wafer LCD of the reflection-type LCD projector, and a method of testing the panel pixel area of the silicon wafer LCD display. The present invention can be applied to LCD display panels manufactured by CMOS process and polysilicon thin film transistor process for the benefits of helping to resolve manufacturing issues during the development stage, thereby shortening the required production time schedule, and reducing the production cost.

Method for testing reflection LCD projector and display panel pixel area thereof

A thin-film transistor liquid-crystal display (TFT LCD) driver includes a shift register, a sample and hold circuit, a group block, and a controller. The shift register provides N graded sample clocks. Video signals are delivered to the group block via the sample and hold circuit through the control of the controller. The group block having n groups of N switches transfers a group of N pixel signals from the sample and hold circuit to the display. The display driver of the invention providing n.times.N output lines by using N processing units by virtue of the output distribution of the group block not only reduces circuit space, but also lowers the power consumption requirements.

Thin-film transistor liquid-crystal display driver

A D/A converter with a Gamma correction circuit according to the invention is designed for C-DAC which takes up much less space than the conventional R-DAC and 2-divided C-DAC. Therefore, this D/A converter has advantages of simple design and low cost. Furthermore, users can freely define the shape of a Gamma correction conversion curve to thereby widen application areas by adjusting terminal voltages.

D/A converter with a Gamma correction circuit

A read/write collision-free static random access memory which can perform read/write operations simultaneously without read/write collisions. The static random access memory includes a plurality of memory cells and its features are that the memory cells are divided into several memory banks wherein each bank has independent reading and writing paths. The number of memory cells for each memory bank can be determined by a specific length of memory cells between some memory cells undergoing reading operation and other memory cells undergoing writing operation, and by the reading speed of said reading operation and the writing speed of the writing operation, whereby the reading operation and the writing operation read and write to two different memory banks of the static random access memory at the same time such that read/write collisions can be prevented.

Read/write collison-free static random access memory

A single-port SRAM with no read/write collisions. The present invention uses some X-axis and Y-axis control circuits to reduce the amounts of lines used in the structure of the present invention, but still maintains circuitry stability.

Single-port SRAM with no read/write collisions

The continuing need for faster and denser SRAM memories places a constant increased demand on the power consumption of the memory devices. Much of the power consumption occurs during the pre-charge phase where it is common practice to bring up all pre-charge circuits at once and hold them active until the memory operations are complete. This invention describes a design where each pre-charge circuit connected to a group of memory cells through bit lines is activated at a separate time from the other pre-charge circuits. Thus each pre-charge circuit is active only during the time that useful work is being done with that portion of the memory. This reduces power consumption by not powering on circuits and precharging bit lines before they are actually needed.

Reduced power consumption sram

A clock control circuit for sequentially enabling the clock input terminal of a number of groups of shift register stages for reducing the power consumption. The groups are seccessively activated, and the groups currently not in operation are made not to consume power. During changeover between adjacent groups of shift register stages, the clocks for the different groups overlap to insure stable operation.

Shift register system for driving active matrix display

The apparatus of the present invention is a CMOS digital level shifter circuit which includes an inverter connected to a voltage generator. The voltage generator comprises an NMOS source follower connected to a directional switching element and a voltage regulating capacitor. The level shifter further includes a latch energized by the same voltage supply energizing the voltage generator. Each branch of the latch has a complementary MOS transistor pair with common gates connected to the output of the inverter and to the input signal respectively. Each complementary transistor pair is connected to the voltage supply by a latch transistor whose gate is cross-connected to the complementary transistor pair of the other branch. Whenever the one transistor in each complementary pair which is connected to ground is on, the latch transistor is latched off by the complementary transistor pair in the other branch after each voltage transition by the input signal, thereby reducing or eliminating DC power consumption, while requiring only a single voltage supply.

Growing community of inventors

Hsinchu, Taiwan

Nang-Ping Tu