Gigadevice Semiconductor (beijing) Inc.

Gigadevice Semiconductor Inc.

Nanfei Wang

Baokui Li

Jinghua Wang

Ze He

Yingwu Zhang

Disclosed are a memory operating method, memory and electronic device. The memory follows a read-write parallel protocol and includes a plurality of memory banks, and the method comprises: writing data to a specified location of the first memory bank corresponding to a current logical address, and pre-reading original data in a specified location of the second memory bank corresponding to a next logical address in a current clock cycle; encoding the pre-read original data and data to be written next, when an instruction to encode based on the pre-read original data in a next clock cycle is obtained; and writing the encoded data to the specified location of the second memory bank in the next clock cycle. By pre-reading the original data corresponding to the incremental address in the current clock cycle, the present disclosure can accelerate an encoding operation that may occur next.

Memory operation method for unaligned write, memory and electronic device

Disclosed are a memory operating method, memory and electronic device. The memory complies with a read-write parallel protocol and includes a plurality of memory banks, and the method includes: sequentially mapping read and write transactions for consecutive logical addresses to different banks according to a predetermined transmission bit width by an address decoder, and arbitrating the read transaction and write transaction mapped to the same bank in a current clock cycle by an arbitration circuit, wherein in case that a specific low address bits of the logical address are the same, the read and/or the write transaction are mapped to the same bank. The disclosure avoids long-term occupation of a certain physical bank with specific low address decoding solution, thereby improving the execution efficiency of the read-write parallel protocol. Furthermore, an arbitration mechanism is introduced to arbitrate read and write conflicts for the same memory bank in each clock cycle.

Memory operating method, memory and electronic device

An information protection method and device based on a plurality of sub-areas for an MCU chip, the MCU chip comprises an instruction bus, a data bus, a flash controller and a user area of a flash memory, the method comprises: determining a preceding sub-area when the instruction bus accesses the user area; entering corresponding preceding sub-area working state; determining the current sub-area when the instruction bus accesses the user area; when the preceding sub-area is inconsistent with the current sub-area, entering the transition state; determining whether the duration of the transition state reaches the preset waiting time; if yes, entering the corresponding current sub-area working state. The information protection method and device prevent the cooperative companies which develop the program together from stealing program from each other.

Information protection method and device based on a plurality of sub-areas for MCU chip

A flash controller and a control method for the flash controller. The flash controller comprises an instruction bus interface, a data bus interface, a configuration register, an erase access filter module, a read/write access filter module and a flash control module. The read/write access filter module is configured to receive control information and determine whether the read/write access is sent to the flash control module or not. The erase access filter module is configured to receive control information and determine whether the erase access is sent to the flash control module or not. The flash control module is configured to complete an access to a flash memory. The present disclosure is used to protect programs from being stolen by a client, and also protect against a situation where companies collaboratively developing a program are able to steal programs from one another.

Flash controller and control method for flash controller

The disclosure discloses a method and a device of information protection for a micro control unit (MCU) chip, the MCU chip comprises an instruction bus, a data bus, a flash controller and a user area of a flash memory; the flash controller is used to divide the user area into a first sub-area and a second sub-area; the method comprising: when the instruction bus accesses the user area, determining, whether the instruction bus accesses the first sub-area; if yes, entering the first sub-area working state; in the first sub-area working state, if the instruction bus accesses the second sub-area, entering the transition state; determining whether the time at transition state reaches a preset waiting time; if yes, entering the second sub-area working state; the disclosure is used to protect program from being stolen by users and prevent the cooperative companies stealing program from each other.

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Beijing, China

Nanfei Wang