Applied Micro Circuits Corporation

Macom Technology Solutions Holdings, Inc.

Macom Connectivity Solutions, LLC

Nanda Govind Jayaraman

Yehuda Azenkot

Tarun Gupta

Echere Iroaga

A voltage regulator operable to selectively supply an extended range of regulated voltages by using multiple levels of unregulated voltages and a single amplifier. The voltage regulator is coupled to a plurality of passing elements in parallel via enabling switches. Each passing element is configured to receive a respective level of unregulated voltage and, when enabled, can pass current to the voltage regulator and thereby induce a corresponding level of regulated voltage at the output terminal of the voltage regulator. To output a specific regulated voltage, the voltage regulator can operate in a single passing mode in which only the passing element receiving the corresponding unregulated voltage is enabled to pass current. Alternatively, in a parallel passing mode, two or more passing elements receiving different levels of unregulated voltages can be enabled to pass current.

On-chip voltage regulator providing extended range of voltage supplies

An interleaved DAC utilizes a set of positive sub-DACs and a set of negative sub-DACs for converting digital inputs in parallel without return to zero. For each digital input, a positive sub-DAC performs conversion and drives its analog output for a duration of N/f; and a negative sub-DAC performs conversion and drives its analog output for a duration of (N&#x2212;1)/f, and by a delay of 1/f. The positive sub-DAC and the negative sub-DAC start the conversion at the same time. By combining the outputs from the two sets of sub-DACs, the output from the positive sub-DAC is effectively removed when it is no longer needed at the combined output. As a result, the combined analog signal has each data point valid only for a duration of T, thereby achieving the desired data conversion speed of f.

High frequency digital-to-analog conversion by interleaving without return-to-zero

System and method of buffering sampled signals in a time-interleaved analog-to-digital converter (ADC). When the input voltage to the buffer varies to a different level, a constant reset voltage is supplied to the buffer output that drives a large capacitive load, e.g., composed of an array of sub-ADCs. The reset voltage functions to remove the capacitive effect from a previous output value on the load. As a result, the buffer can buffer the input for the load without introducing intersymbol interference (ISI). A reset switch can be used to control the supply of the reset voltage to the buffer output according to a predetermined clock signal. The reset voltage may be the common mode potential in a differential source follower in the buffer. An additional voltage gain can be advantageously achieved by the buffer with a gain factor being independent of the load capacitance.

High speed buffering for time-interleaved ADCS with reduced ISI and increased voltage gain

An interleaved DAC configured to generate a set of second digital inputs responsive to a set of first digital inputs. Each second digital input is obtained by subtracting the other second digital inputs in the set from the corresponding first digital input. Two consecutive first digital inputs are shifted by a phase of T=1/f. The second digital inputs are supplied to a set of sub-DACs arrange in parallel. Each sub-DAC operates at a frequency of f/R, and drives an analog output responsive to each second digital input for a duration of R&#xd7;T. Clock signals used by two sub-DACs for converting two consecutive second digital inputs are offset by a phase of T. In each interval of T, summation of the analog signals output from the set of sub-DACs produces an analog value of a single first digital input, thereby achieving a data conversion speed of f.

High frequency digital-to-analog conversion by time-interleaving without return-to-zero

System and method of calibrating the DC offsets of alternate comparators in an ADC in the background based on the digital outputs of the ADC. In parallel with A/D conversion of a plurality of samples, the calibration logic uses two counters to count the occurrences of the ADC outputs that represent samples falling in a first analog range and a second analog range, respectively. The two ranges are symmetric about the MSB reference voltage and in combination cover the nominal voltage range of the bit. The DC offset is derived based on a ratio of the difference between the two counts and a sum of the two counts. The calibration logic may alternately calibrate the comparators. Each comparator may be calibrated successively based on various bits associated therewith.

DC offset calibration of ADC with alternate comparators

Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the resistor. On applying a control voltage to the third transistor and applying an input voltage to the first control port, the second control port is selectively modified by the control voltage to produce a desired output at the first input port and the second input port.

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Santa Clara, CA, United States of America

Nanda Govind Jayaraman