Spansion Llc.

Advanced Micro Devices Corporation

Other

Fujitsu Corporation

Nancy S Leong

Tiao-Hua Kuo

Johnny C Chen

Yasushi Kasa

Guowei Wang

Hounien Chen

Darlene G Hamilton

Michael Van Buskirk

Sachit Chandra

Yi He

Zhizheng Liu

Ming Sang Kwan

Xuguang Alan Wang

Sung-Yong Chung

Sung-Chul Lee

Yugi Mizuguchi

Aaron Lee

Nian Niles Yang

Takao Akaogi

Michael Allen Van Buskirk

Lee Edward Cleveland

Kazuhiro Kurihara

Binh Quang Le

Yuan Tang

Chung K Chang

Michael A VanBuskirk

Michael David Fliesler

Takao Akagoi

Eric Itakura

May Xie

A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Controlling AC disturbance while programming

A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command including an address for a memory cell in the array of memory cells and an indication regarding whether the read command is a full page read command or a partial page read command. A starting address for a page including the received address is identified, wherein the page includes multiple rows of memory cells in the array of memory cells. The address register is reset to the starting address for the page. It is determined whether all memory cells in the page are non-programmed. Data indicative of a non-programmed state of the page is output if it is determined that all memory cells in the page are non-programmed.

Read mode for flash memory

A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.

Flash memory device having improved program rate

A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

High performance flash memory device capable of high density data storage

A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.

Multi-bit flash memory device having improved program rate

A non-volatile memory, such as a Flash memory, is configured to perform a random multi-page read operation. The memory may include a core array of non-volatile memory cells and input lines for receiving an indication of the random multi-page read operation. Further, the memory may include a multi-level volatile memory coupled to the core array that is configured to simultaneously process multiple pages of data from the core array in a pipelined manner. Output lines are coupled to the multi-level volatile memory and output the pages of data from the memory device.

Random cache read using a double memory

A method for programming a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes performing a program operation on a group of memory cells, where the group of memory cells includes a plurality of subgroups. A verify status value is stored for each subgroup, the verify status value indicating a verify status of each subgroup, wherein the verify status value indicates whether an associated subgroup has been program verified. A program verify operation is performed on a selected subgroup when the verify status value associated with the selected subgroup indicates that the selected verify subgroup has not been program verified.

Program and program verify operations for flash memory

A bank selector encoder comprises a partition indicator circuit having a plurality of partition boundary indicator terminals, a plurality of inverters arranged in a plurality of columns, with each column of the inverters coupled to a respective one of a plurality of columns of ROM cells in a ROM array and a plurality of bank selector code outputs coupled to respective columns of the inverters. The partition boundary indicator terminals are capable of designating a memory partition boundary to identify an upper memory bank and a lower memory bank. The bank selector encoder is capable of generating an identifying bank selector code for each of a plurality of the predetermined memory partition boundaries. The bank selector encoder outputs code bits of a bank selector code based upon the partition boundary indicator terminals.

Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture

A multiple purpose bus for a flash memory device that allows six sets of data signals to utilize the bus. The multiple purpose bus includes sixteen circuit lines that extend from one end of the memory device to another end of the memory device. Control signals that correspond to each set of data signals couple the sets of data signals to the circuit lines. A grounding circuit is provided that couples the circuit lines to a ground when none of the sets of data signals are utilizing the multiple purpose bus.

Multiple purpose bus for a simultaneous operation flash memory device

A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option, a bank selector encoder coupled to receive a memory partition indicator signal from the memory boundary option, and a bank selector decoder coupled to receive a bank selector code from the bank selector encoder. The decoder, upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.

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Sunnyvale, CA, United States of America

Nancy S Leong