Rambus Inc.

Nancy David Dillon

Frederick Abbott Ware

Craig Edward Hampel

Mark A Horowitz

Ely K Tsern

Richard Maurice Barth

Donald C Stark

Donald Victor Perino

James A Gasbarro

Billy Wayne Garrett, Jr

Matthew Murdy Griffin

William Franklin Stonecypher

Michael Tak-Kei Ching

Andy Peng-Pui Chan

A socket () includes a first bus conductor (a) having two or more contact regions () and a second bus conductor (b) arranged substantially parallel to the first bus conductor and having two or more contact regions (). The first and second bus conductors are spaced relative to one another so as to provide a predetermined electrical impedance and may be arranged to carry electrical signals as transmission lines. A dielectric spacer () may be disposed between the first and second bus conductors to provide the spacing. Contact regions () of the first and second conductors (a,b) may provide compliant coupling regions for the socket (). The contact regions () of the first bus conductor (a) may be positioned within the socket () so as to contact a lead disposed on a first side of a circuit element () and the contact regions () of the second bus conductor (b) may be positioned within the socket () so as to contact the lead disposed on the second side of the circuit element ().

Connector with integral transmission line bus

A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

Apparatus and method for pipelined memory operations

An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (), an analog voltage divider (), an input comparator (), a sampling latch (), a current control counter (), and a bitwise output driver (output driver Aand output driver B).

Memory system including a memory device having a controlled output driver characteristic

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Washington, VA, United States of America

Nancy David Dillon