International Business Machines Corporation

Macronix International Co., Ltd.

Nanbo Gong

Takashi Ando

Guy M Cohen

Alexander Reznicek

Bahman Hekmatshoartabari

Ruilong Xie

Hsiang-Lan Lung

Heng Wu

Cheng-Wei Cheng

Franco Stellari

Robert L Bruce

Matthew Joseph BrightSky

Christopher P Miller

Wei-Chih Chien

Yulong Li

Seyoung Kim

Tayfun Gokmen

Kevin W Brew

Wanki Kim

A non-volatile memory apparatus includes a first hydrogen reservoir, which is electrically conductive; a charge of hydrogen, which is captured in the first hydrogen reservoir; a dielectric layer that has a first side that is adjacent to the first hydrogen reservoir and a second side that is opposite from the first hydrogen reservoir; a second hydrogen reservoir that is adjacent to the second side of the dielectric layer, is electrically conductive, and has a side that is opposite from the dielectric layer; and a piezoelectric layer that is adjacent to the side of the second hydrogen reservoir and that has a side that is opposite from the second hydrogen reservoir.

Piezoelectric memory

Embodiments of the present invention include a phase change memory (PCM) array. The PCM array may include a plurality of PCM cells. Each PCM cell in the plurality of PCM cells may include a top electrode, a resistive element, and a bottom electrode. The PCM array may also include a global heater surrounding the plurality of PCM cells having a thermally conductive material contacting each of the plurality of PCM cells. The global heater may be configured to receive an electric signal to heat the plurality of PCM cells simultaneously.

Global heater for phase change memory

A method for system authentication includes subjecting a system to a challenge. The method further includes receiving a response from the system. The received response is dependent upon a location of a filament in a resistive random-access memory device of the system. Additionally, the response is also a unique identifier.

RRAM filament location for physically unclonable function

A tunable nonvolatile resistive element, wherein the device conductance is modulated by changing the length of a contact between a phase change material and a resistive liner. By choosing the contact length to be less than the transfer length a linear modulation of the conductance is obtained.

Transfer length phase change material (PCM) based bridge cell

In an approach to a implementing a PUF based on a PCM array, for each PCM device in an array of PCM devices, the PCM device is reset to an initial state. A first conductance of the PCM device is measured. A predetermined number of partial set pulses is applied to the PCM device. A second conductance of the PCM device is measured. Responsive to determining that the second conductance is greater than the first conductance multiplied by a factor, a PUF value of the PCM device is set to logical '1'. Responsive to determining that the second conductance is less than the first conductance multiplied by a factor, a PUF value of the PCM device is set to logical “0”. The PUF value of the PCM device is added to an overall PUF string for the array of PCM devices.

Physically unclonable function based on a phase change material array

An apparatus comprises a phase-change material, a first electrode at a first end of the phase-change material, a second electrode at a second end of the phase-change material, and a heating element coupled to a least a given portion of the phase-change material between the first end and the second end. The apparatus also comprises a first input terminal coupled to the heating element, a second input terminal coupled to the heating element, and an output terminal coupled to the second electrode.

Phase-change material-based XOR logic gates

A circuit structure includes a first ferroelectric field effect transistor (FeFET) having a first gate electrode, a first source electrode, and a first drain electrode and a second FeFET having a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode is connected to a wordline, and the first source electrode and the second source electrode are connected to a bitline. The first drain electrode is connected to the second gate electrode and the second drain electrode is connected to a bias line. A weight synapse structure is constructed by combining two circuit structures. A plurality of weight synapse structures are incorporated into a crossbar array.

FeFET unit cells for neuromorphic computing

A device includes a non-volatile analog resistive memory cell. The non-volatile analog resistive memory device includes a resistive memory device and a select transistor. The resistive memory device includes a first terminal and a second terminal. The resistive memory device has a tunable conductance. The select transistor is a ferroelectric field-effect transistor (FeFET) device which includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the FeFET device is connected to a word line. The source terminal of the FeFET device is connected to a source line. The drain terminal of the FeFET device is connected to the first terminal of the resistive memory device. The second terminal of the resistive memory device is connected to a bit line.

Non-volatile analog resistive memory cells implementing ferroelectric select transistors

An embodiment of the invention may include a semiconductor structure, method of use and method of manufacture. The structure may include a heating element located underneath a temperature-controlled portion of the device. A method of operating the semiconductor device may include providing current to a thin film heater located beneath a temperature-controlled region of the semiconductor device. The method may include performing temperature dependent operations in the temperature-controlled region.

Temperature-assisted device with integrated thin-film heater

A semiconductor structure comprises a gate structure of a transistor. The gate structure comprises a gate conductive portion disposed on a gate dielectric layer. The semiconductor structure further comprises a capacitor structure disposed on the gate structure. The capacitor structure comprises a first conductive layer, a dielectric layer disposed on the first conductive layer and a second conductive layer disposed on the dielectric layer. The first and second conductive layers are respectively connected to a first contact portion and a second contact portion.

Transistor gates having embedded metal-insulator-metal capacitors

An approach for representing both positive and negative weights in neuromorphic computing is disclosed. The approach leverages a double gate FeFET (ferroelectric field effect transistor) device. The device leverages a double-gate FeFET with four terminals (two separate gates and source and drain) and ferroelectric gate dielectric. The device may have a junction-less channel. A synaptic weight is programmed by biasing one of the two gates. The store weight is sensed via a current flow from source to drain. A pre-defined bias is applied to the other gate during the sensing, such that a reference current is subtracted from the drain current. The net current for sensing is current from the synaptic devices subtracted by the pre-defined reference current.

FeFET with double gate structure

A method for forming a nonvolatile PCM logic device may include providing a PCM film component having a first end contact distally opposed from a second end contact, positing a first proximity adjacent to a first surface of the PCM film component, positing a second proximity heater adjacent to a second surface of the PCM film component, wherein the first proximity heater and the second proximity heater are electrically isolated from the PCM film component. The method may further include applying a combination of pulses to one or more of the first proximity heater and the second proximity heater to change a resistance value of the PCM film component corresponding to a logic truth table. Further, the method may include simultaneously applying a first combination of reset pulses to program, or set pulses to initialize, the PCM film component, to the first proximity heater and the second proximity heater.

Nonvolatile phase change material logic device

A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.

Phase change memory cell with ovonic threshold switch

A semiconductor device is provided. The semiconductor device includes a resistive memory device, and at least a first photodetector and a second photodetector positioned adjacent to the resistive memory device to allow for measurement of the intensity of photon emission from a filament of the resistive memory device.

ReRAM analog PUF using filament location

A random number generator comprising resistive random-access memory (RRAM) devices including: a first electrode; a second electrode; a third electrode located between the first and second electrode; at least one electrically insulating layer separating the first electrode and the second electrode from the third electrode, wherein the at least one electrically insulating layer has a substantially uniform thickness; a first filament that is current conducting and extends through the at least one electrically insulating layer; a second filament is located in the at least one electrically insulating layer and does not extend through the at least one electrically insulating layer; a voltage source configured to apply voltage to at least one of the first electrode and the second electrode; and a voltage sensor configured to sense voltage of the third electrode in order to determine which one of the first filament or the second filament is more resistive.

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White Plains, NY, United States of America

Nanbo Gong