Freescale Semiconductor,inc.

Nan Xu

Jinzhong Yao

Zhigang Bai

Xingshou Pang

Xuesong Xu

Bin Tian

Zhijie Wang

Wai Wong Chow

Hei Ming Shiu

Qingchun He

Junhua Luo

Zhi-gang Bai

Shufeng Zhao

Zhe Li

Yongsheng Lu

Guanhua Wang

Xue-song Xu

Jin-zhong Yao

A method for assembling a packaged semiconductor device includes mounting a pressure-sensing die onto a die paddle of a metal lead frame. A pressure-sensitive gel is dispensed into a recess of a lid, and the lead frame is mated with the lid such that the pressure-sensing die is immersed in the pressure-sensitive gel within the recess of the lid.

Packaged semiconductor sensor device with lid

A Quad Flat Non-leaded (QFN) semiconductor package has a semiconductor die mounted on a die flag of a lead frame. A molded housing with a base and sides covers the die. The package has electrically conductive mounting feet each of which includes an exposed base surface in the base of the housing, an opposite parallel surface covered by the housing, and an exposed end surface in the one of the sides of the housing. The exposed end surface is normal to, and located between, the exposed base surface and the opposite parallel surface. Bond wires selectively electrically connect electrodes of the die to respective ones of the mounting feet. An electrically conductive plating coats the exposed base portion and exposed end surface of the mounting feet.

Quad flat non-leaded semiconductor package with wettable flank

A method of assembling semiconductor devices includes placing an array of semiconductor dies on a die support. A cap array structure is provided that has a corresponding array of caps supported by a cap frame structure. The cap array structure and the array of semiconductor dies on the die support are aligned, with the caps extending over corresponding semiconductor dies, in a mold chase. The array of semiconductor dies and the array of caps are encapsulated with a molding compound in the mold chase. The encapsulated units of the semiconductor dies with the corresponding caps are removed from the mold chase and singulated. Singulating the encapsulated units may include removing the cap frame structure from the encapsulated units.

Method of packaging semiconductor die with cap element

A process for assembling a Chip-On-Lead packaged semiconductor device includes the steps of: mounting and sawing a wafer to provide individual semiconductor dies; performing a first molding operation on a lead frame; depositing epoxy on the lead frame via a screen printing process; attaching one of the singulated dies on the lead frame with the epoxy, where the die attach is done at room temperature; and curing the epoxy in an oven. Throughput improvements may be ascribed to not including a hot die attach process. An optional plasma cleaning step may be performed, which greatly improves wire bonding quality and a second molding quality. In addition, since a first molding operation is performed before the formation of epoxy to avoid the problem of the epoxy hanging in the air, the delamination risk between the epoxy and the die is avoided.

Method of making chip-on-lead package

A method for assembling a semiconductor package includes a rapid cooling step after post mold curing of an encapsulation material. The rapid cooling step includes blowing chilled, compressed air over the package for about two minutes. The rapid cooling step does not require any clamping pressure be simultaneously applied to the package. The rapid cooling step reduces a temperature of the encapsulation material from a curing temperature to the cooled temperature within a maximum period of less than five minutes. By using rapid cooling, as opposed to cooling the package under a clamping pressure with ambient air, package warpage due to CTE mismatches is prevented.

Method for making semiconductor package

A lead frame for reducing detrimental effects of burr formation includes a lead frame that has leads where a portion of a top surface is removed from a first lead and a portion of a bottom surface is removed from a second lead adjacent to the first lead to reduce spacing between leads while reducing the detrimental effects of burr formation, such as shorting and the like, caused during singulation of a semiconductor device manufactured with the lead frame.

Lead frame for semiconductor device

In a method of packaging a semiconductor IC, a tape is attached to a back surface of a lead frame array, and the lead frame array is held between an upper mold chase and a lower mold chase of a mold, with the back surface of the lead frame array upward. The upper and lower mold chases form an upper cavity and a lower cavity with respect to the lead frame array respectively. A mold compound is injected into the upper and lower cavities respectively. With respect to clearances between leads, between die pads and/or between the leads and the die pads, the mold compound injected into the upper cavity covers the portion of the tape over the clearances before the mold compound injected into the lower cavity fills the clearances, so that the tape is depressed. After curing the mold compound, removing the mold and de-taping, the mold compound filled in the clearances is recessed inward from the back surface, which increases the solderability in the subsequent surface mount process and decreases the possibility of the occurrence of lead short-circuits.

Semiconductor integrated circuit package and method of packaging semiconductor integrated circuit

A method of forming a pre-molded lead frame having increased stand-offs includes the steps of attaching a first tape to a first side of the lead frame and a second tape to a second side of the lead frame. The taped lead frame is placed in a mold and a first flow of mold compound is initiated. The first flow of the mold compound fills a space between the first tape and an upper mold chase of the mold. A second flow of the mold compound then is initiated. The second flow of the mold compound fills the spaces between a die pad and leads of the lead frame. The first and second tapes then are removed from the lead frame. Improved stand-offs are provided because the first tape was depressed by the first flow of the mold compound.

Method of forming premolded lead frame

A method of packaging an integrated circuit die () includes the steps of forming an array of soft conductive balls () in a fixture () and flattening opposing sides of the balls. The flattened balls are then transferred from the fixture to a mold masking tape (). A first side of the IC die is attached to the balls with a die attach adhesive () and then wire bonding pads () on the die are electrically connected directly to respective balls with wires (). An encapsulant () is formed over the die, the electrical connections, and a top portion of the formed balls. The tape is removed and adjacent, encapsulated dice are separated via saw singulation. The result is an encapsulated IC having a bottom side with exposed balls.

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Tianjin, China

Nan Xu