Semiconductor Manufacturing International (Shanghai) Corporation

Semiconductor Manufacturing International (Beijing) Corporation

Honeywell International Inc.

Semiconductor Manufacturing (Shanghai) International Corporation

Semiconductor Manufacturing (Beijing) International Corporation

Shanghai Hua Hong Nec Electronics Company, Limited

Dell Products Inc.

Alcatel Lucent

Coupang, Corporation

Other

Cisco Technology, Inc.

Nokia Solutions and Networks Oy

Fudan University

Baidu (China) Co., Ltd.

Dow Global Technolgoies LLC

Nan Wang

Orville Nyhus

Yu Chen

Chao Wang

He Wang

Yonggang Wang

Hua Chao

Bin Gu

Xin Zhi Ma

Ke Ma

Xu Yang

Xiaohong Chen

Xiang Yao

Christopher Carlson

Shixian Li

Guoyou Feng

Shixiong Fan

Yachen Wang

Qimeng Lu

Jian Ding

Austin Michael Shelnutt

Liang Jie Xu

Xin Xu

Qing Xu

Pingping Xing

Zhongji Hu

Jun Zhu

Xun Sun

Yang Sun

Chao Zhang

Xiaolian Hu

Fei Huang

Gong Zhang

Yanli Feng

Zhe Jiang

Yun Bai

Zhong Shan Hong

Charles Chao Wang

Xiaohua Cheng

Cheng Qian

Zhikun Wan

Bruce Chen

Biao Ma

Zongchuang Liang

Chen Zhong

Guifeng Song

Shouke Qin

Zhan Ying

Jianwen Yao

You Han

Peizhi Xu

Binxin Liu

Xiaosong Li

Chunli Chen

Zhongmin Gan

Zhaogui Li

Zi Wang

Zi Cheng Pan

Meilin Tang

Ruoyuan Li

Xiaodong Hao

The present invention pertains to the technical field of biomedicine, and relates to isopaucifloral F phosphate compounds and pharmaceutical uses thereof. It has been confirmed through experiments that said isopaucifloral F phosphate compounds and pharmaceutically acceptable salts thereof have effects on the bone remodeling process by exerting their anti-osteoporosis efficacy through a dual-mode mechanism of action of promoting osteogenesis and reducing osteoclast resorption, have the characteristics of high bioavailability, stable metabolism and good safety, and can be used to prepare a new generation of anti-osteoporosis drugs.

Isopaucifloral F phosphate compound and pharmaceutical use thereof

Semiconductor device and fabrication method are provided by providing initial fins discretely arranged on a substrate; forming an isolation structure on the substrate; forming a connecting layer on sidewalls of the initial fins and between adjacent initial fins; forming a dummy gate structure across the initial fins and the connecting layer on the substrate, covering sidewalls of the connecting layer and a portion of a top surface of the initial fins; forming grooves in the initial fins on both sides of the dummy gate structure, and forming source and drain doped layers in the grooves; forming a dielectric layer on the substrate, covering sidewalls of the dummy gate structure and the source and drain doped layers, that a top surface of the dielectric layer is flush with a top surface of the dummy gate structure; and removing the dummy gate structure to form a gate structure.

Semiconductor device and fabrication method thereof

Semiconductor structures is provided. The semiconductor structure includes a semiconductor substrate having at least one first region, a plurality of second regions and a plurality of third regions; at least one second fin formed on one second region of the plurality of second region; at least one third fin formed on one third region of the plurality of third regions; a first epitaxial layer formed in the at least one first fin; and a second epitaxial layer formed in the at least one second fin and the at least one third fin.

Semiconductor structure

The present invention provides an offline handwriting individual recognition system and method. The method comprises: scanning the suspicious handwriting to obtain a first white light image and a first three-dimensional image, and scanning the sample handwriting to obtain a second white light image and a second three-dimensional image; pre-processing the first white light image and the second white light image to obtain a first pre-processed image and a second pre-processed image; extracting a first skeleton image and a second skeleton image from the first pre-processed image and the second pre-processed image; obtaining a first writing trajectory and a second writing trajectory according to the first skeleton image and the second skeleton image; extracting a first dynamic feature, a first three-dimensional feature, and a second dynamic feature, a second three-dimensional feature; processing to obtain a correlation coefficient, and obtaining an individual recognition result.

Offline handwriting individual recognition system and method based on three-dimensional dynamic features

A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a base substrate; a gate structure on the base substrate, including a first portion in a first region and a second portion in a second region; and one or more stop layers on the base substrate and located in the first portion of the gate structure in the first region. A length of the first portion of the gate structure in the first region is larger than a length of the second portion of the gate structure in the second region.

A semiconductor device and a fabrication method are provided. The semiconductor device includes: a base substrate; a gate structure on the base substrate including a first portion in a first region and a second portion in a second region; and a separation section in the first portion of the gate structure in the first region. A length of the first portion of the gate structure in the first region is larger than a length of the second portion of the gate structure in the second region. A top surface of the separation section is higher than a top surface of the gate structure.

The invention provides an offline handwriting individual recognition system and method based on two-dimensional dynamic features. The method comprises: obtaining a first handwriting image corresponding to suspicious handwriting and second handwriting images corresponding to a plurality of sample handwriting; pre-processing the first handwriting image and the second handwriting images to obtain a first pre-processed image and second pre-processed images; extracting a first skeleton image and second skeleton images from the first pre-processed image and the second pre-processed images; obtaining a first writing trajectory and second writing trajectories according to the first skeleton image and the second skeleton images; extracting first dynamic features and second dynamic features according to the first writing trajectory and the second writing trajectories; performing processing to obtain a correlation coefficient between the suspicious handwriting and the sample handwriting, and performing processing to obtain an individual recognition result according to the correlation coefficient.

Offline handwriting individual recognition system and method based on two-dimensional dynamic features

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, including a plurality of protrusions; a plurality of fins formed over the substrate and aligned with the plurality of protrusions; and an isolation structure formed on the substrate and between the protrusions and the fins. An orthographic projection of each of the plurality of fins and an orthographic projection of a corresponding protrusion of the plurality of protrusions on the substrate coincide with each other.

Semiconductor device

A semiconductor device is provided. The semiconductor device includes a base substrate; and a first gate structure and doped source/drain layers on the base substrate. The doped source/drain layers are on both sides of the first gate structure. The semiconductor device further includes a dielectric layer on a surface of the base substrate. The dielectric layer covers the doped source/drain layers, and the dielectric layer contains a first trench on the doped source/drain layer. The first trench includes a first region filled by an insulation layer and a second region filled by first conductive structure under the insulation layer. A top size of the insulation layer in the first region is larger than a bottom size of the insulation layer in the first region. A maximum size of the first conductive structure in the second region is smaller than the bottom size of the insulation layer in the first region.

Semiconductor device with conductive structure and insulation layer of different width

A static random-access memory device is provided. The static random-access memory device includes a substrate with at least one first region; first fins on a surface of the substrate, and second initial fins on the surface of the substrate. A width of the second initial fins is different from a width of the first fins. A portion of the first fins is used to form pass-gate transistors, and another portion of the first fins and the second initial fins are used to form pull-down transistors.

Static random-access memory and fabrication method thereof

A semiconductor structure and its fabrication method are provided. The method includes: providing a substrate; forming an isolation structure on the substrate; forming a gate structure on the isolation structure; forming a first opening in the gate structure; and forming a first conductive structure in the first opening. Sidewall surfaces of the first conductive structure are in contact with a gate electrode layer of the gate structure.

Semiconductor structure and fabrication method thereof

A semiconductor device is provided. The semiconductor device includes a base substrate; a gate structure on the base substrate; source/drain doped layers in the base substrate on sides of the gate structure; a first dielectric layer on the base substrate and covering the source/drain doped layers; a mask layer on a top of the gate structure between the source/drain doped layers; a second dielectric layer on the first dielectric layer and exposing a surface of the mask layer; first grooves in the second dielectric layer and the first dielectric layer, and exposing the source/drain doped layers; a first conductive structure in each first groove; a second groove in the mask layer, and exposing the gate structure at a bottom of the second groove; and a spacer on sidewalls of the second groove.

Semiconductor device with isolation between conductive structures

A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a substrate; a gate structure on the substrate and extending along a first direction; source/drain doped layers in the substrate at sides of the gate structure; a first conductive structure on the source/drain doped layers; an opening at a top of the gate structure and the first conductive structure; and a second conductive structure in the opening. The opening extends along a second direction and the second direction is different from the first direction. The second conductive structure is insulated from the first conductive structure and in contact with the gate structure.

The embodiments of the present disclosure provide systems and methods for outbound forecasting, comprising receiving an initial distribution of priority values to each fulfillment center (FC) in each region, running a simulation, using a simulation algorithm, of the initial distribution, calculating an outbound capacity utilization value of each FC, determining a number of FCs comprising an outbound capacity utilization value that exceeds a predetermined threshold, feeding the simulation algorithm with the determined number of FCs to generate one or more additional distributions of priority values, generating a FC priority filter comprising an optimal set of priority values based on the one or more additional distributions of priority values, and modifying an allocation of a plurality of SKUs among a plurality of FCs based on the generated FC priority filter.

Systems and methods for outbound forecasting based on a fulfillment center priority value

A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a substrate, and forming a first core layer on the substrate. The substrate includes a pull-up transistor region. The method also includes forming separately arranged second core layers on the first core layer, and forming a first sacrificial sidewall spacer on a sidewall of a second core layer. A gap is formed between adjacent first sacrificial sidewall spacers over the pull-up transistor region. In addition, the method includes removing the second core layers, and then etching the first core layer using the first sacrificial sidewall spacers as a mask until the substrate is exposed. The gap is transferred to a region between adjacent etched first core layers over the pull-up transistor region. Further, after etching the first core layer, the method includes forming a dielectric layer to fully fill the gap.

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Shanghai, China

Nan Wang