Mediatek Corporation

Nan-Cheng Chen

Che-Ya Chou

Wen-Chou Wu

Yen-Ju Lu

Wen-Sung Hsu

Tung-Hsien Hsieh

Chih-Ming Hung

Shih-Chieh Lin

Sheng-Ming Chang

Ching-Chih Li

Tao Cheng

Hsing-Chih Liu

Che-Hung Kuo

Wei-Hsiu Hsu

Min-Chen Lin

Yang Liu

Ying Liu

Nan-Jang Chen

Shih-Chia Chiu

Hui-Chi Tang

Fu-Kang Pan

Fu-Yi Han

Chih-Tai Hsu

Chun-Wei Chang

Chih-Hui Kuo

Che-Yuan Jao

Chia-Hao Yang

Jui-Hsing Tseng

Shih-Yi Syu

Chia-Yu Jin

Kun-Ting Hung

Pei-San Chen

A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.

Semiconductor device

A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, a molding compound disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the molding compound. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.

Antenna-in-package with frequency-selective surface structure

A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

Semiconductor package with layer structures, antenna layer and electronic component

One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

Semiconductor package having discrete antenna device

A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, an encapsulation layer disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the encapsulation layer. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.

A semiconductor package is provided. The semiconductor package includes a semiconductor device bonded to a base through a first conductive structure. The semiconductor device includes a carrier substrate including a conductive trace. A portion of the conductive trace is elongated. The semiconductor device also includes a second conductive structure above the carrier substrate. A portion of the second conductive structure is in contact with the portion of the conductive trace. The semiconductor device further includes a semiconductor body mounted above the conductive trace. The semiconductor body is connected to the second conductive structure.

Semiconductor package using flip-chip technology

A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.

Semiconductor package

An over-the-air (OTA) wireless test system includes a container, a machine plate disposed on the container, a supporter disposed on the machine plate, a load board disposed on the supporter, a socket disposed on the load board, a device under test (DUT) installed in the socket, and a wave-guiding feature in the socket and the load board configured to pass and guide electromagnetic waves to and/or from an antenna structure of the DUT. The wave-guiding feature comprises a wave-guiding channel in the socket defined by a plurality of pogo pins surrounding the antenna structure of the DUT. The wave-guiding feature may further comprise a radiation passage in the load board defined by rows of via fence extending through an entire thickness of the load board.

Over the air wireless test system for testing microelectronic devices integrated with antenna

A semiconductor package structure is provided. The semiconductor package structure includes a first carrier substrate having a first surface and an opposing second surface. A second carrier substrate is stacked on the first carrier substrate and has a first surface and an opposing second surface that faces the first surface of the first carrier substrate. A semiconductor die is mounted on the first surface of the second carrier substrate. A heat spreader is disposed on the first surface of the first carrier substrate to cover and surround the second carrier substrate and the semiconductor die. A method for forming the semiconductor package structure is also provided.

Fan-out package structure having stacked carrier substrates and method for forming the same

A semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure.

Fan-out package structure

A semiconductor package is provided. The semiconductor package includes a carrier substrate having opposite first surface and second surface, and a chip stack disposed on the first surface of the carrier substrate. The chip stack includes a first semiconductor die, a second semiconductor die, and an interposer between the first semiconductor die and the second semiconductor die. The interposer transmits signals between the first semiconductor die and the second semiconductor die.

Semiconductor package incorporating redistribution layer interposer

A layout method for a printed circuit board (PCB) is provided. The method obtains a memory type of a dynamic random access memory (DRAM) to be mounted on the PCB, obtains a module group from a database according to the memory type of the DRAM, wherein the module group comprises a plurality of routing modules, obtains a plurality of PCB parameters, selects a specific routing module from the module group according to the PCB parameters, and implements the specific routing module into a layout design for PCB fabrication. The specific routing module comprises layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip.

Layout method for printed circuit board

A printed circuit board for mobile platforms includes a core substrate having a first side, a ground plane covering on the first side, a first insulating layer covering the ground plane, and a plurality of first signal traces and a plurality of first ground traces, alternatively arranged on the first insulating layer, a second insulating layer connecting to the first insulating layer, and a plurality of second signal traces separated from each other, disposed on the second insulating layer, wherein the second signal traces are disposed directly on spaces between the first signal traces and the first ground traces adjacent thereto, wherein coverage of the ground plane is corresponding to disposition of the first signal trace, the first ground trace, the second signal trace and the second ground trace.

Growing community of inventors

Hsin-Chu, Taiwan

Nan-Cheng Chen