Lg Display Co., Ltd.

Namwook Cho

Changsoo Kim

Cheolhwan Lee

Hyoung-Su Kim

JaeMyon Lee

Euitae Kim

TaeHwan Kim

BuYeol Lee

Soyi Lee

Kiseob Shin

KiSeob Shin

JaeHee Park

Bu Yeol Lee

Sanghyeon Kwak

Doohyun Yoon

Aram Shin

Hyoungsu Kim

Hyuntaek Lim

Junbae Son

Myungjae Yoo

Buyeol Lee

A display apparatus includes a display panel including an active area that includes at least one module area and a bezel area positioned outside the active area, wherein a pixel array is positioned in the active area, and the at least one module area is formed as a light-transmissive area.

Display apparatus

A transparent display apparatus for preventing the occurrence of a sense of difference between a display panel and a cover substrate is provided. The transparent display apparatus includes a transparent display panel including a first substrate, a second substrate, and a plurality of pixels provided between the first substrate and the second substrate, a display area including the plurality of pixels, and a non-display area surrounding the display area and a cover substrate including a first area overlapping the transparent display panel and a second area surrounding the first area and including a plurality of dummy patterns.

Transparent display apparatus having a plurality of dummy patterns

In a transparent display panel, a layer of each of a VSS voltage connection line and a VDD voltage connection line as a power line in a display region is different from a layer of a data line and a reference voltage connection line, while each of the VSS voltage connection line and the VDD voltage connection line partially overlaps the data line and the reference voltage connection line. Thus, an overall width of a line region may be reduced. Thus, an area of a pixel circuit region is reduced, such that an area of a transmissive region increases, thereby to increase an overall transmittance of the panel. Further, a width of each of the VSS voltage connection line and the VDD voltage connection line is large while reducing or minimizing an area of the line region in the display region. This reduces or minimizes occurrence of VDD drop or VSS rise, thereby to reduce luminance non-uniformity of the panel.

Transparent display panel and transparent display device including the same

Disclosed is a transparent display device that includes a plurality of column lines and a plurality of horizontal lines crossing each other to define a plurality of pixel regions in a matrix, each column line including at least two data lines and a voltage line, and each horizontal line including a gate line; a first transparent electrode in each emission region; a transparent organic light emitting layer on the first electrode; and a second transparent electrode on the organic light emitting layer, wherein each pixel region includes a transmissive region and a circuit region, and wherein the transmissive region includes at least two emission regions that are divided by a first transparent bank pattern.

Transparent display device

A see-through organic light emitting display device including a light emitting region having a transparent anode, an organic light emitting layer, and a transparent cathode, and a see-through region having a transparent auxiliary electrode, which is configured to transmit external light. The transparent auxiliary electrode can be made from the same material as the transparent anode and separated from the transparent anode, and the transparent cathode extends into the see-through region so as to be electrically connected with the transparent auxiliary electrode.

See-through organic light emitting display device and method for manufacturing the same

An organic light emitting display is provided. The organic light emitting display comprises a multi-type thin-film transistor (TFT) and an organic light emitting diode. The multi-type TFT has a low-temperature-poly-silicon (LTPS) TFT and an oxide semiconductor TFT (oxide TFT) disposed on the LTPS TFT. The organic light emitting diode is electrically connected to the multi-type TFT. The LTPS TFT and the oxide TFT are connected to the same gate line.

Display backplane and method of fabricating the same

There is provided a TFT backplane having at least one TFT with oxide active layer and at least one TFT with poly-silicon active layer. In the embodiments of the present disclosure, at least one of the TFTs implementing the circuit of pixels in the active area is an oxide TFT (i.e., TFT with oxide semiconductor) while at least one of the TFTs implementing the driving circuit next to the active area is a LTPS TFT (i.e., TFT with poly-Si semiconductor).

Display having selective portions driven with adjustable refresh rate and method of driving the same

Disclosed is an OLED display device. The OLED display device includes a metal line and a thin film transistor that are formed on a substrate, a first insulating layer formed on the metal line and the thin film transistor, a storage electrode formed on the first insulating layer, and connected to the metal line, a second insulating layer formed on the storage electrode, and an anode electrode formed on the second insulating layer to be connected to the thin film transistor and overlapping the storage electrode with the second insulating layer therebetween.

Organic light emitting diode display device and method of manufacturing the same

A display device comprises a display panel in which data lines and gate lines cross each other, a timing controller which outputs a single gate pulse modulation control signal ('FLK signal') and I-phase (where I is an integer equal to or more than 2) gate shift clocks which are sequentially delayed, an FLK dividing circuit which divides the single FLK signal to output J (where J is an integer equal to or more than 2 and smaller than I) FLK signals, a data driving circuit which converts digital video data into data voltages to supply the data voltages for the data lines, and a gate driving circuit which generates gate pulses by level-shifting voltages of the gate shift clocks, to modulate falling edge voltages of the gate pulses in response to the divided FLK signals, and to sequentially supply the modulated gate pulses for the gate lines.

Growing community of inventors

Paju-si, South Korea

Namwook Cho