Samsung Electronics Co., Ltd.

Namsung Kim

Sukhan Lee

Seongil O

Kyomin Sohn

Shinhaeng Kang

Jaeyoun Youn

Hak-Soo Yu

Daemyung Chun

Youngcheon Kwon

Jaiwon Jean

Joongseo Kang

Kijun Lee

Hak-soo Yu

Jonghyun Lee

Sanguhn Cha

Yesin Ryu

Kiwon Park

Byungchul Choi

Youngsub Shin

A memory device includes a memory bank including one or more bank arrays, a PIM circuit configured to perform an operation logic processing operation, and an instruction memory including first to minstruction queue segments configured in a circular instruction queue to store instructions provided by a host, where instructions stored in the first to minstruction queue segments are executed in response to an operation request from the host and each new instruction provided by the host is written over a completely executed instruction in the circular instruction queue.

Memory device and method including processor-in-memory with circular instruction memory queue

A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.

Memory device for processing operation, data processing system including the same, and method of operating the memory device

A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.

Method of performing internal processing operations with pre-defined protocol interface of memory device

A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.

Memory device, a controller for controlling the same, a memory system including the same, and a method of operating the same

A semiconductor light-emitting device includes a buffer structure, a first-type semiconductor layer on the buffer structure, an active layer on the first-type semiconductor layer, and a second-type semiconductor layer on the active layer. The buffer structure includes a nucleation layer, a first dislocation-removing structure on the nucleation layer, and a buffer layer on the first dislocation-removing structure. The first dislocation-removing structure includes a first material layer on the nucleation layer and a second material layer on the first material layer. The second material layer has a lattice constant different from a lattice constant of the first material layer. A roughness of a top surface of the first material layer is higher than a roughness of a top surface of the nucleation layer and higher than a roughness of a top surface of the second material layer.

Semiconductor light-emitting device including buffer structure

Managing memory device with processor-in-memory circuit to perform memory or processing operation

A semiconductor light emitting device including a semiconductor laminate having first and second surfaces, the semiconductor laminate including first and second conductivity-type semiconductor layers, and an active layer between the semiconductor layers; a partition structure on the first surface, the partition structure having a window defining a light emitting region of the first surface of the semiconductor laminate; a wavelength converter in the window, the wavelength converter being configured to convert a wavelength of light emitted from the active layer; and a first electrode and a second electrode on the second surface of the semiconductor laminate and respectively connected to the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, wherein the semiconductor laminate includes a plurality of first patterns arranged in the light emitting region of the first surface, and a plurality of second patterns arranged in a covered region of the first surface contacting the partition structure.

Semiconductor light emitting device

A semiconductor memory device including: a buffer die; memory dies stacked on the buffer die; and TSVs, at least one of the memory dies includes: a memory cell array; an error correction code (ECC) engine; an error information register; and a control logic circuit configured to control the ECC engine to perform a read-modify-write operation, wherein the control logic circuit is configured to: record, in the error information register, a first address associated with a first codeword based on the an generation signal and a first syndrome obtained by an ECC decoding; and determine an error attribute of the first codeword based on a change of the first syndrome, recorded in the error information register, based on a plurality of read-modify-write operations.

Semiconductor memory devices

A high bandwidth memory and a system having the same are disclosed. The high bandwidth memory includes a buffer die and a plurality of memory dies, each of which includes at least one first processing element bank group and at least one second processing element bank group. The at least one first processing element bank group includes one or more first banks connected to one or more first bank input/output line groups, and a first processing element controller connected to the one or more first bank input/output line groups and a first global input/output line group, and is configured to perform a first processing operation on first data output from one of the one or more first bank input/output line groups and second data transmitted through the first global input/output line group based on a first instruction that is generated based on a first processing command.

High bandwidth memory and system having the same

A memory device includes a memory bank including at least one bank group, a processor in memory (PIM) circuit including a first processing element arranged to correspond to the bank group, which processes operations by using at least one of data provided by a host and data read from the bank group, a processing element input and output (PEIO) gating circuit configured to control electric connection between a bank local IO arranged to correspond to each bank of the bank group and a bank group IO arranged to correspond to the bank group, and a control logic configured to perform a control operation so that a memory operation for the memory bank is performed or operations are processed by the PIM circuit. When the operations are processed by the first processing element, the PEIO gating circuit blocks the electric connection between the bank local IO and the bank group IO.

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Yongin-si, South Korea

Namsung Kim