Samsung Electronics Co., Ltd.

Namjong Kim

Taeyoung Oh

Chulsung Park

Suyeon Doo

A semiconductor memory device includes a memory circuit including a plurality of memory cells and a refresh control circuit. The refresh control circuit is configured to determine a number of times to perform a target row refresh (TRR) in response to a mode register set (MRS) code signal, wherein the MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle of at least two of the memory cells for a period of time when the refresh cycle is changed due to the temperature change.

Semiconductor memory device that includes a refresh control circuit that maintains a refresh cycle when an MRS code signal is changed due to temperature

Growing community of inventors

Suwon-si, South Korea

Namjong Kim