Samsung Electronics Co., Ltd.

Seoul National University

Namhyung Kim

Dohan Kim

Insu Choi

Deokho Seo

Daejeong Kim

Kiyoung Choi

Seungwon Lee

Changmin Lee

Wonjae Shin

Hanmin Park

Minsu Kim

Chanik Park

Ilguy Jung

Hoyoung Lee

Woong Seo

Wonho Lee

Jaehoon Lee

Chijoon Kim

Jihoon Kang

Jonghwan Choi

Changyong Seo

Gunhee Lee

Sangbong Lee

Junwhan Ahn

Kiyul Lim

Chinam Kim

Soonwan Chung

Joonsang Yu

Seokki Kim

Jaein Song

Taekon Kim

Taekyeong Ko

Byeongnoh Kim

Bobae Kim

Kyeongjin Cho

A memory system including a memory device that receives a plurality of signals including a post package repair (PPR) command from a host, wherein the memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a plurality of redundancy memory cells connected to one or more redundancy word lines and the plurality of bit lines, and anti-fuse memory cells, and a PPR control circuit that transmits to the host whether a PPR operation on a defective memory cell of the memory cell array has passed.

Memory system, operating method of the same, and controller of memory device

A memory device includes; a memory cell array, and a command/address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command/address information, and a second decoding logic circuit configured to decrypt an address table. The command/address decoder is configured to decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command, decrypt data received from the memory controller after a predefined latency from receipt of the first command through the second decoding logic circuit to obtain an address table, store the address table in the buffer memory, decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the address table, and execute the table-based command with respect to an address corresponding to the index information.

Memory device including address table and operating method for memory controller

A processor-implemented method of processing neural network data includes: setting first limit data by performing a first operation based on first input data and weight data generated from weights included in a filter; comparing the first limit data with an intermediate result of a second operation performed based on second input data and the weight data; and determining whether to perform a subsequent second operation based on a result of the comparing.

Method and apparatus with data processing

Disclosed is a foldable electronic device including a sealing member for protecting a side surface of flexible display. A foldable electronic device according to various embodiments of the disclosure may include: a foldable housing configured to be folded and unfolded, a flexible display disposed in the foldable housing, the flexible display including a display panel configured to display image information and a cover window covering a first surface of the display panel on which image information is displayed, the display panel having at least one portion configured to be bent according to folding and unfolding operations of the foldable housing, and a seal contacting a region of a side part of the flexible display with reference to the first surface of the flexible display, the region including a space between the cover window and the display panel, wherein the seal may include a polymer material which is configured to be bent according to the bending operation in a state of being in contact with a side surface of the flexible display during the bending operation of the flexible display.

Electronic device including display side protection member

A method of accelerating a training process of a neural network includes acquiring activations used in the training process and a bit-vector corresponding to the activations, selecting activations requiring an operation from among the acquired activations by using the bit-vector, and performing backward propagation using the selected activations and filters corresponding to the selected activations.

Method of accelerating training process of neural network and neural network device thereof

A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.

Memory device, memory module including the memory device, and operating method of memory controller

A memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into multiple regions. The test controller is configured to perform a parallel bit test (PBT) on the plurality of memory cells, where the test controller selects fail data including a fail data bit among internal data output from the multiple regions during the PBT, and outputs the fail data via a data input/output signal line to the outside of the memory device.

Memory device capable of outputting fail data in parallel bit test and memory system including the memory device

Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

Accelerator controlling memory device, computing system including accelerator, and operating method of accelerator

Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row.

Memory device skipping refresh operation and operation method thereof

An electronic device according to certain embodiments includes a housing, a first glass plate coupled to the housing and defining an inner space, the first glass plate including a peripheral portion including: a first, second, third, fourth, and fifth surface forming an edge of the glass plate, the first and fifth surfaces being substantially parallel and the third surface being substantially perpendicular to the first and fifth surfaces, a decorative layer formed of a first material, disposed on a first area of the fifth surface such that a second area disposed between the fourth surface and the first area is uncovered by the decorative layer, and a protective layer formed of a second material, covering the second surface, the third surface, the fourth surface, the second area of the fifth surface, and a part of the decorative layer.

Electronic device including glass plate

A method of managing a cache includes storing first data of an upper level cache in a lower level cache, predicting a reuse distance level of second data having a same signature as the first data based on access information about the first data, and storing the second data in one of the lower level cache and a main memory based on the predicted reuse distance level of the second data.

Computing apparatus and method for cache management

Growing community of inventors

Seoul, South Korea

Namhyung Kim