Stmicroelectronics Pvt. Ltd.

Other

Stmicroelectronics International N.v.

Sicronic Remote Kg, LLC

Namerita Khanna

Parvesh Swami

Ashish Kumar Goel

Deepak Agarwal

Davinder Aggarwal

Ankur Bal

Rajnish Garg

Rohit Kumar Gupta

A device includes input data lines associated with a first time domain and output data lines associated with a second time domain. Synchronizing circuitry is coupled between the input data lines and output data lines. The synchronizing circuitry is driven by a synchronizing clock signal generated by clock generating circuitry. The clock generating circuitry is coupled to the input data lines and the synchronizing circuitry. In operation, the clock generating circuitry detects signal transitions on the plurality of input data lines. The clock generating circuitry generates the synchronizing clock signal that drives the synchronizing circuitry based on detected transitions, a clock signal of the first time domain, and a clock signal of the second time domain.

Device with low-power synchronizing circuitry and related method

In at least some embodiments, a Programmable Logic Device (PLD) is configured to using a counter in conjunction with a threshold value to determine whether a configuration data frame is to be reloaded into a frame register if errors are encountered. In at least other embodiments, a Programmable Logic Device (PLD) is configured to sequentially load configuration data frames into a frame register, check for errors in the configuration data frames during sequentially loading, and correct errors during sequentially loading without reloading one or more previously-loaded different configuration data frames.

Processing configuration data frames

An improved programmable logic device provides increased efficiency and enhanced flexibility in configuration of block memories and includes one or more memory blocks and a vertical shift register that receives the data to be loaded in the memory blocks. The PLD further provides a selection device for selecting the memory cells in the memory blocks that are to store the received data, and a control block for controlling the loading of the data in the memory blocks. The selection device includes an address counter connected to the input of an address decoder so as to enable the selection of addresses in the memory blocks.

Programmable logic devices

An improved method and apparatus for reloading frames in which errors are detected during the Programmable Logic Device configuration. A configuration data frame for a FPGA is loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An error counter value is maintained by the apparatus and is incremented each time an error with a frame is detected. The incremented value is compared by a Comparator circuit with a pre-determined threshold value 'n'. If a match is found then the configuration process is aborted, else the data frame is reloaded in the configuration memory, transferred again to the frame register and rechecked for errors. If no error is detected with the reloaded frame, the error counter value is reset and the next frame is loaded until the FPGA configuration process is over.

Method and apparatus of reloading erroneous configuration data frames during configuration of programmable logic devices

An improved Programmable Logic Device architecture that provides more efficient utilization of resources by enabling access to defined circuit elements in the domain of any Programmable Logic Block (PLB) from any other PLB in the device, by incorporating a connecting means in the routing structure for selectively connecting the input or output of the circuit element in the domain of the PLB to the common interconnect matrix connecting all the PLBs together.

Architecture for programmable logic device

A Programmable Logic Device providing reduction in power consumption for sequential logic and data storage functions, including at least one circuit arrangement configurable to function as a dual-edge-triggered flip-flop operating on a selected one or both edges of the circuit clock.

Programmable logic devices providing reduced power consumption

This invention relates to a high performance interconnect architecture providing reduced delay minimized electro-migration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.

High performance interconnect architecture for field programmable gate arrays

An electronic circuit containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation. The electronic circuit includes an improved clock distribution scheme that reduces power consumption, comprising identifying means for determining the select/deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.

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New Delhi, India

Namerita Khanna