Globalfoundries Singapore Pte. Ltd.

Namchil Mun

Shiang Yang Ong

Jeoung Mo Koo

Raj Verma Purakh

Purakh Raj Verma

Ming Li

Francis Lionel Benistant

Ke Dong

Kun Liu

Tat Wei Chua

Mun Tat Yap

Hung Chang Liao

Zhongxiu Yang

Jianbo Zhou

Semiconductor structures including a deep trench isolation structure and methods of forming a semiconductor structure including a deep trench isolation structure. The semiconductor structure includes a semiconductor substrate having a device region, and a deep trench isolation structure in the semiconductor substrate. The deep trench isolation structure further includes a first portion, a second portion adjacent to the first portion, and a conductor layer in the first portion and the second portion. The conductor layer in the first portion of the deep trench isolation structure surrounds the device region. The conductor layer in the second portion of the deep trench isolation structure defines an electrical connection to the semiconductor substrate.

Deep trench isolation structures with a substrate connection

Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. The structure includes a drift well in a semiconductor substrate, source and drain regions in the semiconductor substrate, a gate dielectric layer on the semiconductor substrate, and a buffer dielectric layer on the semiconductor substrate over the drift well. The buffer dielectric layer includes a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first section extending from the second side edge to the first side edge, and a plurality of second sections extending from the second side edge toward the first side edge. The first section has a first thickness, and the second sections have a second thickness less than the first thickness. A gate electrode includes respective portions that overlap with the buffer dielectric layer and with the gate dielectric layer.

Laterally-diffused metal-oxide-semiconductor devices with a multiple-thickness buffer dielectric layer

The present invention discloses a Schottky diode. The Schottky diode comprises a substrate having a device well. A drift region is disposed within the device well. A guard ring region is disposed within the device well and adjacent to the drift region. A field isolation region and a dielectric film are disposed on a top substrate surface. The dielectric film is aligned to the field isolation region. A field plate is disposed over the field isolation region and the dielectric film. The field plate completely covers a top surface of the dielectric film and partially overlaps the guard ring region. A conductive contact layer is disposed adjacent to the dielectric film. The conductive contact layer contacts a portion of the device well to define a Schottky diode interface.

High voltage Schottky diode and manufacturing method thereof

A high voltage transistor with low on resistance is disclosed. The transistor may include at least one cut out region in the drift region under the drain of the transistor. The cut out region is devoid of the drift well which connects the drain to the channel. Cut out regions may be distributed along the width direction of the drain region of the transistor. The transistor may alternatively or further include a vertical polysilicon plate surrounding the device region. The vertical polysilicon plate may be implemented as a deep trench isolation region. The deep trench isolation region includes a deep trench lined with an insulation collar and filled with polysilicon. The vertical polysilicon plate reduces an on resistance to improve device performance.

Low on resistance high voltage metal oxide semiconductor transistor

The present disclosure relates to semiconductor structures and, more particularly, to contact structures to deep trench isolation structures and methods of manufacture. The structure includes: a deep trench structure lined with insulator material on sidewalls thereof; conductive material filling the deep trench structure; a local oxide extending above the trench on exposed portions of the insulator material; an interlevel dielectric material on the local oxide and the conductive material filling the deep trench structure; and a contact in the interlevel dielectric material, extending to the conductive material and on a side of the local oxide.

Contact structures to deep trench isolation structures and method of nanufacturing the same

VDMOS transistors, Bipolar-CMOS-DMOS (BCD) devices including VDMOS transistors, and methods for fabricating integrated circuits with such devices are provided. In an example, a BCD device having a VDMOS transistor includes a buried layer over a substrate and an epitaxial layer over the buried layer and having an upper surface. Deep trench isolation regions extend from the upper surface of the epitaxial layer, into the substrate, and isolate a VDMOS region from a device region. In the VDMOS region, a source region is adjacent the upper surface, a vertical gate structure extends into the epitaxial layer, a body region is located adjacent the vertical gate structure and forms a channel, and a VDMOS conductive structure extends through the epitaxial layer and into the buried layer, which is a drain for the VDMOS transistor. The VDMOS conductive structure is a drain contact to the buried layer.

VDMOS transistors, BCD devices including VDMOS transistors, and methods for fabricating integrated circuits with such devices

Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, a method of producing an integrated circuit includes determining a guard ring width within an integrated circuit design layout, where a guard ring with the guard ring width surrounds an active area in the integrated circuit design layout. A deep trench location is calculated for replacing the guard ring, where the deep trench location depends on the guard ring width. The guard ring in the integrated circuit design layout is replaced with a deep trench having the deep trench location. The deep trench is formed within a substrate at the deep trench location, where the deep trench surrounds the active area.

Integrated circuits with deep trench isolations and methods for producing the same

Semiconductor device isolation and method of forming thereof are presented. A base substrate with lightly doped first polarity type dopants is provided. A buried layer with heavily doped second polarity type dopants is formed in a top portion of the substrate while an epitaxial layer is formed over the buried layer. First and second type deep trench isolation (DTI) structures which extend from surface of the epitaxial layer to a portion of the base substrate are formed to isolate different device regions defined in the substrate. The first and second type DTI structures have different width dimensions. Shallow trench isolation (STI) regions are formed in the epitaxial layer and at least one transistor is formed on the epitaxial layer. The first and second type DTI structures effectively isolate the transistor from other device regions and enhances the breakdown voltage.

Growing community of inventors

Singapore, Singapore

Namchil Mun