Seeq Technology, Incorporated

Xaqti, Corporation

Vitesse Semiconductor Corporation

Xaqtu Corporation

Namakkal S Sambamurthy

Linh Tien Truong

Alak K Deb

Praveen D Kumar

John P VanGilder

Woo-Ping Lai

Devendra K Tripathi

Alak Deb

Devendra Kumar Tripathi

William H Bares

Disclosed is a media access controller for transferring data along a computer network. The media access controller includes a transmit media access controller that is configured to process out-going packet data received from an upper layer for transmission to a lower layer. A receive media access controller that is configured to process in-coming packet data received from the lower layer for transmission to the upper layer. A transmit multi-packet queue FIFO for receiving the out-going packet data from the upper layer before being passed to the transmit media access controller. A receive multi-packet queue FIFO for receiving the in-coming packet data that is received by the receive media access controller. The media access controller further including a media access controller manager interfacing with the transmit and receive media access controllers. The media access controller manager being responsible for managing the flow of packet data through the transmit and receive multi-packet queue FIFOs.

Media access control architectures and network management systems

Disclosed are methods and apparatus for processing packet data received from a physical layer. The processing is performed in-line while streaming packets to an upper layer. The method includes loading an instruction set for custom programming the processing of packet data received from the physical layer. Determining a type of packet data received from the physical layer. Identifying a first word location in the packet data based on the contents of the instruction set. Examining the packet data received from the physical layer at the first identified word location. The method further includes storing an element indicative of information contained in the first identified word location into a data structure, and appending the data structure to the packet data before the packet is streamed to the upper layer. The methods and apparatus also have direct applicability to reducing a CPU's work load during transmissions of data over a network.

Media access control micro-RISC stream processor and method for implementing the same

Disclosed is a media access controller for transferring data along a computer network. The media access controller includes a transmit media access controller that is configured to process out-going packet data received from an upper layer for transmission to a physical layer. A receive media access controller that is configured to process in-coming packet data received from the physical layer for transmission to the upper layer. A transmit multi-packet queue FIFO for receiving the out-going packet data from the upper layer before being passed to the transmit media access controller. A receive multi-packet queue FIFO for receiving the in-coming packet data that is received by the receive media access controller. The media access controller further including a media access controller manager interfacing with the transmit and receive media access controllers. The media access controller manager being responsible for managing the flow of packet data through the transmit and receive multi-packet queue FIFOs.

Disclosed is a transmit media access controller having a transmit interface unit configured to receive packet data, transfer control signals and control information from an upper layer. The transmit media access controller also includes a transmit controller for processing the packet data based on the control information received from the upper layer. The transmit control block is bi-directionally coupled to the transmit interface unit. While the packet data is being processed, new control information may be received by the in communication with the transmit controller. The transmit media access controller further includes an interface unit configured to receive packet data from the transmit cyclic redundancy check unit before being transmitted to a physical layer.

Media access control transmitter and parallel network management system

Disclosed is a media access controller configured to communicate with an upper layer and a lower physical layer. The media access controller includes a receive controller for receiving and processing receive data requests from the lower layer and transferring received data to the upper layer. The method includes receiving data from the lower layer and processing the received data through the receive controller. The processor being performed in accordance with a setting of a plurality of control registers associated with the transmit controller. The method further including receiving a control signal for modifying at least one of the plurality of control registers while the data is being processed through the receive controller. Altering the processing of data being processed within the receive controller based on the modification of the at least one of the plurality of control registers associated with the receive controller, and transferring the processed data to the upper layer.

Media access control receiver and network management system

A downward compatible full-duplex ethernet transceiver associated with either the hub or the remote node in an ethernet local area network (LAN) includes generator circuitry for generating a full-duplex-capability signal indicating its full-duplex capability for transmission over a link of the LAN and detector circuitry for detecting transmission of such a signal from the transceiver with which it is communicating across the link of the LAN. The detector circuitry responds to the full-duplex-capability signal by sending a full-duplex enable signal to an ethernet controller configured according to the present invention. An ethernet controller contains circuitry responsive to the full-duplex-enable signal to disable transmission deferral in response to a carrier-sense signal generated by the transceiver. The full-duplex-capability indicator portion may comprise an extra pulse following an Nth link-integrity pulse after a delay of from about 2 to about 7 microseconds.

Apparatus and method for full-duplex ethernet communications

A downward compatible full-duplex 10Base-T ethernet transceiver associated with both the hub or the remote node in an ethernet network includes generator circuitry for generating a full-duplex-capability signal indicating its full-duplex capability for transmission over the twisted pair link and detector circuitry for detecting transmission of such a signal from the transceiver with which it is communicating across the twisted pair link. The detector circuitry responds to the full-duplex-capability signal by sending a full-duplex enable signal to an ethernet controller configured according to the present invention. An ethernet controller contains circuitry responsive to the full-duplex-enable signal to disable transmission deferral in response to a carrier-sense signal generated by the transceiver. The full-duplex-capability indicator portion may comprise an extra pulse following an Nth link-integrity pulse after a delay of between about 2-7 .mu.sec.

A downward compatible full-duplex 10Base-T ethernet transceiver associated with either the hub or the remote node in an ethernet network includes generator circuitry for generating a full-duplex-capability signal indicating its full-duplex capability for transmission over the twisted pair link and detector circuitry for detecting transmission of such a signal from the transceiver with which it is communicating across the twisted pair link. The detector circuitry responds to the full-duplex-capability signal by sending a full-duplex enable signal to an ethernet controller configured according to the present invention. An ethernet controller contains circuitry responsive to the full-duplex-enable signal to disable transmission deferral in response to a carrier-sense signal generated by the transceiver. The full-duplex-capability indicator portion may comprise an extra pulse following an Nth link-integrity pulse after a delay of between about 2-7 .mu.sec.

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San Jose, CA, United States of America

Namakkal S Sambamurthy