Skhynix Inc.

Nam Young Ahn

Kyung Hoon Kim

Eung Bo Shim

Yong Tag Song

Hyun Jung Park

A machine learning device including a general-purpose memory module interface is disclosed. The machine learning device includes a data storage circuit configured to store raw data and command data received from a host device through a memory module interface, and store machine learning data as a result of machine learning of the raw data and location data of the machine learning data, a machine learning logic circuit configured to generate the machine learning data through the machine learning of the raw data according to a pre-programmed machine learning logic, and a machine learning controller configured to read the raw data from the data storage circuit based on the command data, transmit the read raw data to the machine learning logic circuit, and write the machine learning data and the location data in the data storage circuit.

Machine learning device and machine learning system using the same

A computing system includes: a memory device including a memory cells; a memory controller configured to control the memory device; and a host configured to detect an occurrence of an error in a first memory cell of the memory device while performing an operation corresponding to a workload and transmit, to the memory controller, a target address corresponding to the first memory cell and a request for a test operation on adjacent memory cells that are adjacent to the first memory cell. The memory controller controls the memory device to perform the test operation on the adjacent memory cells by using at least one of a Built-In Self-Test (BIST) engine or a scrub engine based on the target address and generate memory error information including information associated with a second memory cell in which the error occurs, the second memory cell being one of the adjacent memory cells. The host controls an access to the second memory cell based on the memory error information.

Computing system and operating method thereof

A data processing system comprising: a memory system comprising a plurality of memory devices, each of which comprises a first error correction unit and a plurality of cell array regions each having a plurality of memory cells coupled in an array to a plurality of word lines and a plurality of bit lines; and a host comprising a second error correction unit for correcting an error of data transferred from the memory system, and suitable for generating error correction information on the error correction operation of the second error correction unit, setting error correcting strengths to the respective memory devices using the error correction information and log information, and performing counter-error operations on the respective memory devices according to the error correcting strengths.

Memory system for selecting counter-error operation through error analysis and data process system including the same

A semiconductor system may include a host, a memory controller and a memory apparatus. The host may generate a mirror request when a program requiring a mirroring operation is executed. The memory controller may generate mirror information based on the mirror request. The memory apparatus may dynamically perform the mirroring operation based on the mirror information.

Memory apparatus, memory module and semiconductor system capable of dynamic mirroring

A memory module may be provided. The memory module may include a normal memory device, a spare memory device, and a row hammering determination circuit. The row hammering determination circuit may be configured to control the spare memory device to perform a data input and output operation, instead of a data input and output operation with the normal memory device in which row hammering has occurred.

Growing community of inventors

Seoul, South Korea

Nam Young Ahn