Samsung Electronics Co., Ltd.

Nam-su Lim

Jae-Kwan Park

Byung-jun Hwang

So-wi Jin

Jang-ho Park

Dong-hwa Kwak

Dong-Hwa Kwak

Jee-Hoon Han

In-Wook Oh

Jong-sun Sel

A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction.

Methods of manufacturing NAND flash memory devices

Semiconductor devices having wiring with contact pads and dummy lines

A semiconductor device or a memory which includes the same have a line pattern, and a contact plug, the line pattern including a first linear feature to which the contact plug is connected by design, and a second linear feature having a connecting portion and a dummy portion adjacent the location at which the contact plug is electrically connected to the first linear feature. A second contact plug is electrically connected to the connecting portion of the second linear feature of the line pattern. In the case of a misalignment error or the like, the first contact plug may also be electrically connected to the second linear feature of the line pattern but at the dummy portion thereof so as to not create a short circuit in that case. The dummy portion thus allows a sufficiently large process margin to be secured for the contact plug.

Semiconductor device including dummy

Nonvolatile memory devices that utilize dummy word line segments to inhibit dishing during fabrication

NAND flash memory devices having wiring with integrally-formed contact pads and dummy lines and methods of manufacturing the same

A NAND flash memory device includes a plurality of active regions extending in a first direction on a substrate, the active regions including a first well of a first conductivity, a plurality of word lines extending on the first well in a second direction perpendicular to the first direction, first and second dummy word lines extending in a second direction on the first well, the first and second dummy word lines being separated from each other to define an intermediate region therebetween, the first and second dummy word lines being adapted to receive a substantially constant bias voltage of about 0 V, and at least one contact in an active region in the intermediate region between the first and second dummy word lines.

NAND flash memory device having a contact for controlling a well potential

Growing community of inventors

Hwaseong-si, South Korea

Nam-su Lim