Samsung Electronics Co., Ltd.

Nam Seog Kim

Dong Hyeon Jang

Sa Yoon Kang

Yong Hwan Kwon

Heung Kyu Kwon

Ho Jin Lee

In Young Lee

Tae Gyeong Chung

Ha Young Yim

A microelectronic structure includes a conductive pad on a substrate. The conductive pad includes first and second openings extending therethrough. A first conductive via on the conductive pad extends through the first opening in the conductive pad into the substrate. A second conductive via on the conductive pad adjacent the first conductive via extends through the second opening in the conductive pad into the substrate. At least one of the conductive vias may be electrically isolated from the conductive pad. Related devices and fabrication methods are also discussed.

Microelectronic devices including multiple through-silicon via structures on a conductive pad and methods of fabricating the same

In accordance with the present invention, a chip scale package (CSP) is manufactured at wafer-level. The CSP includes a chip, a conductor layer for redistribution of the chip pads of the chip, one or two insulation layers and multiple bumps, which are interconnected to respective chip pads by the conductor layer and are the terminals of the CSP. In addition, in order to improve the reliability of the CSP, a reinforcing layer, an edge protection layer and a chip protection layer are provided. The reinforcing layer absorbs stress applied to the bumps when the CSP is mounted on a circuit board and used for an extended period, and extends the life of the bumps, and thus, the life of the CSP. The edge protection layer and the chip protection layer prevent external force from damaging the CSP. After forming all elements constituting the CSP on the semiconductor wafer, the semiconductor wafer is sawed to produce individual CSPs.

Chip scale packages manufactured at wafer level

A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film. The semiconductor package includes: an integrated circuit having chip pads; a substrate attached to the integrated circuit so that via holes of the substrate are above the chip pads; solder fillings inside the via holes, the solder fillings electrically connecting the chips pads to the pattern metal layer; and another dielectric layer between the substrate and the semiconductor integrated circuit. The semiconductor package further includes external terminals, interconnection bumps on the chip pads, and polymer protection layers on the solder fillings.

Semiconductor package

method for manufacturing a semiconductor package

An apparatus for identifying a known good die according to an embodiment of the present invention includes a carrier for containing a bare semiconductor chip, a lid for covering the carrier, and a stopper for sealing the apparatus. The carrier includes: a body, in which a chip mount cavity and multiple vacuum suction holes are formed; inner connection terminals formed on a bottom surface of the chip mount cavity to communicate electrically with the bare chip; and outer connection terminals extending from the inner connection terminals to outside the body. The apparatus has an outer configuration of a conventional semiconductor package, so that the apparatus can fit into conventional test equipment. Therefore, the carrier can have a configuration of a plastic package, such as the SOP or SOJ, without a semiconductor chip. Accordingly, the apparatus according to the present invention can use conventional handling and burn-in test equipment in identifying of known good dies and thereby reduce production cost of the known good dies.

Apparatus and method for containing semiconductor chips to identify known good dies

In accordance with the present invention, a chip scale package (CSP) is manufactured at wafer-level. The CSP includes a chip, a conductor layer for redistribution of the chip pads of the chip, one or two insulation layers and multiple bumps, which are interconnected to respective chip pads by the conductor layer and are the terminals of the CSP. In addition, in order to improve the reliability of the CSP, a reinforcing layer, an edge protection layer and a chip protection layer is provided. The reinforcing layer absorbs stress applied to the bumps when the CSP are mounted on a circuit board and used for an extended period, and extends the life of the bumps, and thus, the life of the CSP. The edge protection layer and the chip protection layer prevent external force from damaging the CSP. After forming all elements constituting the CSP on the semiconductor wafer, the semiconductor wafer is sawed to produce individual CSPs.

Growing community of inventors

Kyungki-do, South Korea

Nam Seog Kim