Samsung Electronics Co., Ltd.

Nam-Jong Kim

Young-Sun Min

Jong-Hyun Choi

Ho-Cheol Lee

Hyo-Joo Ahn

Jong-hyun Choi

Hyong-Ryol Hwang

Il-Man Bae

Kyoung-Hwan Kwon

Seouk-Kyu Choi

Dong-Il Seo

Young-Hoon Kim

Chi-Sung Oh

Chang-ho Shin

An internal voltage generator circuit is disclosed. The internal voltage generator circuit includes a comparator configured to compare a first voltage with a reference voltage and to output a comparison signal. The circuit further includes an internal voltage driver configured to receive an external voltage and the comparison signal and to output an internal voltage at an internal voltage output terminal, based on the comparison signal. The circuit further includes a voltage divider circuit including first and second resistor units and a first voltage output terminal between the first and second resistor units, configured to receive the internal voltage, and configured to output the first voltage based on the resistance values of the first and second resistor units, the first and second resistor units connected in series, and the first voltage being output through the first voltage output terminal. The circuit further includes a control signal generator circuit configured to generate at least one resistor control signal for controlling the resistance value of the first resistor unit and at least one resistor control signal for controlling the resistance value of the second resistor unit, on the basis of the comparison signal and a precharge command.

Internal voltage generator circuit and semiconductor memory device using the same

A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.

Multi-port semiconductor memory device having variable access paths and method therefor

In one example embodiment, a speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.

Method of operating a semiconductor device and the semiconductor device

A multi-port semiconductor memory device having variable access paths and a method therefore are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.

Multi-port semiconductor memory device having variable access paths and method

A multi-port semiconductor memory device and a signal input/output method therefore are provided. In one embodiment, the multi-port semiconductor memory device includes a plurality of different input/output ports and a memory array. The memory array has at least one memory region that is accessed by using different input/output ports. The different input/output ports include a first input/output port through which a first signal is input/output and a second input/output port through which a second signal different from the first signal is input/output. The memory region is divided into a plurality of memory regions. The invention provides effects of reducing the number of test pins and improving test efficiency.

Multi-port semiconductor memory device and signal input/output method therefor

A semiconductor memory device that includes a memory cell array having a plurality of memory cells that are connected between a bit line pair, which transfers data to the bit line pair, a precharge circuit for precharging the bit line pair to a precharge voltage level during a precharge period, and one or more bit line sense amplifiers which are connected between the bit line pair and detect a voltage difference of the bit line pair to amplify a level of the bit line pair. The semiconductor memory device includes one or more FINFETs.

Semiconductor memory device

A semiconductor memory device and a method therefor for changing an access right to access a shared memory area according to an external command and a refresh mode is provided. In one embodiment, the semiconductor memory device includes a plurality of input/output ports for inputting command signals for first or second mode refresh operation, a memory array divided into a plurality of different memory areas including a shared memory area that is accessible via at least two of the plurality of input/output ports, and a grant control block for assigning an access right to access the shared memory area in response to an external command signal. The grant control block may also generate grant control signals for preferentially assigning the access right to access the shared memory area to the input/output port for inputting the command signals for the first mode refresh operation.

Multi-port semiconductor memory device and method for accessing and refreshing the same

A method of a partial array self-refresh (PASR) operation for a dynamic random-access memory (DRAM) device includes initiating a PASR mode; writing data into a first single cell of a twin cell and inverted data of the data into a second single cell of the twin cell, during a first refresh period of the PASR mode; and concurrently refreshing the first and second single cells that are included in the twin cell, during subsequent refresh periods of the PASR mode following the first refresh period. Embodiments according to the invention can extend the period of refresh operations by applying a PASR technique for a twin cell to a single cell and thereby reduce the power consumption of the refresh operations.

DRAM and method for partially refreshing memory cell array

A method of programming addresses of failed memory locations in a memory device can be provided by generating a plurality of fail address signals corresponding to a plurality of addresses of failed memory locations in the memory device and then programming the plurality of addresses of failed memory locations to programming cells for use by a redundant circuit during read or write operations to the plurality of addresses of failed memory locations.

Methods and circuits for programming addresses of failed memory cells in a memory device

A verifying circuit and a method of repairing a semiconductor device, the verifying circuit of example embodiments may include a first fuse circuit configured to determine whether a first fuse has been programmed, a test signal generating circuit configured to generate a test signal based on a control signal and an output signal from the first fuse circuit, and a second fuse circuit configured to test whether a plurality of second fuses are programmed based on the test signal.

Verifying circuit and method of repairing semiconductor device

An anti-fuse and an anti-fusing method are disclosed. An example embodiment of the present invention is directed to an anti-fuse circuit, including an anti-fuse receiving a first voltage, a pull-up transistor coupled between the anti-fuse and a first node, the pull-up transistor configured to pull up a voltage at the first node to the first voltage when the anti-fuse is in a given operation mode, a pull-down transistor configured to pull down the voltage at the first node to a second voltage in response to a pull-down control signal, the second voltage lower than the first voltage, a voltage level detector configured to compare a detection reference voltage level with a voltage level at the first node to generate a detection output signal and a pull-down control circuit configured to generate the pull-down control signal based on a fuse input signal and the detection output signal.

Anti-fuse circuit and anti-fusing method

A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc&#x3e;Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIand VI, where VI&#x3e;VI; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOand VO, where VO&#x3e;VO, wherein VI&#x3e;VOor VI&#x3c;VO, and wherein VO&#x3e;Vcc and VO&#x3c;Vss.

Level shifter with low leakage current

A temperature detector and method of detecting a shifted temperature provides multiple detected temperature points using a single branch. The temperature detector generates multiple detected temperature points in response to temperature control signals sequentially generated in a single branch. Since a shifted temperature for the single branch is found and a trimming operation in response to the shifted temperature is carried out, the test time is reduced. Various refresh periods can be set in response to various trip point temperatures and thus power consumption of a DRAM can be decreased.

Temperature detector providing multiple detected temperature points using single branch and method of detecting shifted temperature

A power-up reset circuit with reduced power consumption. The resistance of the power-up reset circuit may be adjusted during a power-up operation. The standby current may thereby be reduced, which may reduce the power consumption in the power-up reset circuit.

Power-up reset circuit with reduced power consumption

A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc&#x3e;Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIand VI, where VI&#x3e;VI; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOand VO, where VO&#x3e;VO, wherein VI&#x3e;VOor VI&#x3c;VOlow, and wherein VO&#x3e;Vcc and VO&#x3c;Vss.

Growing community of inventors

Yongin-si, South Korea

Nam-Jong Kim