Skhynix Inc.

Nam Jae Lee

Jin Won Lee

Nam Kuk Kim

Eun Seok Choi

Yu Jin Park

Jung Dal Choi

Sun Young Kim

Myoung Kwan Cho

Jae Young Oh

There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure; a source structure; a channel structure penetrating the stack structure, the channel structure being connected to the source structure; and a first memory layer interposed between the channel structure and the stack structure. The source structure includes a first protrusion part protruding between the first memory layer and the channel structure.

Manufacturing method of a semiconductor device with a stepped memory film

A semiconductor device may include: a first gate structure including first gate lines, a first step structure including first pads, a first gap-fill insulating layer located between the first gate lines and the first step structure, and first wiring lines connecting the first gate lines and the first pads, respectively; and a second gate structure including second gate lines located on the first gate lines, a second step structure located on the first gap-fill insulating layer and including second pads, a second gap-fill insulating layer located on the first step structure, and second wiring lines connecting the second gate lines and the second pads, respectively.

Semiconductor device and manufacturing method of a semiconductor device

A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first and second vertical conductive patterns isolated from each other by a first slit. The semiconductor device may include at least one first half conductive pattern extending toward a first region disposed at one side of the first slit from the first vertical conductive pattern. The semiconductor device may include at least one second half conductive pattern extending toward a second region disposed at the other side of the first slit from the second vertical conductive pattern.

Semiconductor device and method of manufacturing the same

A semiconductor device includes: a substrate with a cell region and a chip guard region, the chip guard region surrounding the cell region; a first chip guard extending over the chip guard region in a first direction; a second chip guard extending over the chip guard region in the first direction, the second chip guard being spaced apart from the first chip guard; and a third chip guard extending over the chip guard region in a second direction, the second direction intersecting the first direction. The first chip guard includes a first end portion, the second chip guard includes a second end portion, and the third chip guard includes a third end portion that is disposed between the first end portion and the second end portion.

Semiconductor device with multi-directional chip guards

There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor device includes: a first stack structure including interlayer insulating layers and first conductive patterns, which are alternately stacked; a second stack structure including a second conductive pattern overlapping with the first stack structure, and a third conductive pattern overlapping with the first stack structure with the second conductive pattern interposed between the first stack structure and the third conductive pattern, the third conductive pattern having an oxidation rate different from that of the second conductive pattern; channel structures penetrating the first stack structure and the second stack structure; and a bit line overlapping with the first stack structure with the second stack structure interposed between the first stack structure and the bit line.

Semiconductor memory device and manufacturing method of the semiconductor memory device

The present disclosure provides a semiconductor memory device. The semiconductor memory device includes a peripheral circuit structure on a semiconductor substrate, a conductive line connected to the peripheral circuit structure, a peripheral circuit side bonding conductive pattern connected to the conductive line, a peripheral circuit side auxiliary bonding conductive pattern spaced apart from the peripheral circuit side bonding conductive pattern, a cell array side bonding conductive pattern contacting the peripheral circuit side bonding conductive pattern, a cell array side auxiliary bonding conductive pattern contacting the peripheral circuit side auxiliary bonding conductive pattern, and a memory cell array connected to the cell array side bonding conductive pattern.

Semiconductor memory device

The present technology provides a semiconductor device. The semiconductor device includes a stack including insulating patterns and conductive patterns stacked alternately with each other, a channel layer including a first channel portion protruding out of the stack and a second channel portion in the stack, and passing through the stack, and a conductive line surrounding the first channel portion, and the first channel portion includes metal silicide.

Semiconductor device and manufacturing method of the semiconductor device

Provided are a semiconductor memory device and manufacturing of the semiconductor memory device. The semiconductor memory device includes a first circuit structure, a first conductive line connected to the first circuit structure, a second conductive line facing the first conductive line, and a second circuit structure overlapping with the first circuit structure with the first and second conductive lines interposed therebetween, the second circuit structure being connected to the second conductive line. One of the first conductive line and the second conductive line has a region protruding toward the other of the first conductive line and the second conductive line.

Semiconductor memory device and manufacturing method of semiconductor memory device

A semiconductor device and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a stacked structure including a plurality of conductive patterns and a plurality of insulating patterns alternately stacked on each other, a cell plug passing through the stacked structure, a select plug coupled to the cell plug, and a select pattern surrounding the select plug, wherein the select pattern includes a first conductive portion and a second conductive portion covering a sidewall and a top surface of the first conductive portion, and wherein the conductive patterns, the first conductive portion, and the second conductive portion include different materials.

Provided herein is a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes a contact pattern including a vertical contact part, and a sidewall contact part extending from the vertical contact part in a direction crossing the vertical contact part, a lower conductive pattern having a hole into which the vertical contact part is inserted, and an upper conductive pattern overlapping a portion of the lower conductive pattern. The upper conductive pattern includes a first side portion in contact with the sidewall contact part, and a second side portion facing the vertical contact part and spaced apart from the vertical contact part.

Manufacturing method of forming a semiconductor memory device with improved structural stability and process defects

There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a first etch stop layer; a source layer on the first etch stop layer; a second etch stop layer on the source layer; a stack structure on the second etch stop layer; and a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure, the channel structure being electrically connected to the source layer. A material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer.

Manufacturing method of semiconductor memory device

There are provided a semiconductor memory device and a manufacturing method thereof. The manufacturing method of the semiconductor memory device includes: forming a preliminary memory cell array that includes a gate stack structure and a channel structure wherein the gate stack structure includes interlayer insulating layers and conductive patterns, alternately stacked on a first substrate, and wherein the channel structure has a first end portion that penetrates the gate stack structure and extends into the first substrate; forming a common source line to be in contact with a second end portion of the channel structure, the common source line formed on a first surface of the gate stack structure; removing the first substrate; and forming a bit line connected to the first end portion of the channel structure on a second surface of the gate stack structure that is opposite of the first surface of the gate stack structure.

Semiconductor memory device and manufacturing method thereof

A memory device and a method of manufacturing the memory device includes a stacked structure having a cell region and a slimming region. The memory device also includes a plurality of vertical channel structures each including memory cells and vertically passing through the stacked structure in the cell region. The memory device further includes a plurality of support structures each having a structure of each of the vertical channel structures and vertically passing through the stacked structure in the slimming region. The plurality of support structures have different heights depending on the shape of the stacked structure in the slimming region.

Memory device and method of manufacturing the same

There is provided a semiconductor memory device including: a substrate having a Complementary Metal Oxide Semiconductor (CMOS) circuit; a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction on the substrate; a channel structure having a first part penetrating the gate stack structure and a second part extending from one end of the first part, the second part extending beyond the gate stack structure; a common source line extending to overlap with the gate stack structure, the common source line surrounding the second part of the channel structure; a memory layer disposed between the first part of the channel structure and the gate stack structure; and a bit line connected to the other end of the first part of the channel structure, the bit line being disposed between the substrate and the gate stack structure.

Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a source structure, a stacked conductive layer that overlaps with the source structure, a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer, a stacked insulating layer disposed between the first and second select conductive layers and the stacked conductive layer, and a separation insulating structure provided between the first select conductive layer and the second select conductive layer.

Growing community of inventors

Cheongju-si, South Korea

Nam Jae Lee