Samsung Electronics Co., Ltd.

Korea University Research and Business Foundation

Nam Hyung Kim

Do-Han Kim

Dae-Jeong Kim

Insu Choi

Deokho Seo

Min Su Kim

Won Jae Shin

Wonjae Shin

Chang Min Lee

Il Gyu Jung

Yong Jun Yu

In Su Choi

Deok Ho Seo

Minsu Kim

Changmin Lee

Yongjun Yu

Ho-Young Reho Lee

Tae-Kyeong Ko

Dae Jeong Kim

Do-han Kim

Kyu Won Choi

Jae Sung Rieh

Do Han Kim

Jong Won Yun

Jong Nam Jun

Mi Jin Kim

An operation method of a memory controller, which is configured to control a memory module including a plurality of memory devices and at least one error correction code (ECC) device, is provided. The method includes reading a data set including user data stored in the plurality of memory devices and ECC data stored in the at least one ECC device, based on a read command and a first address, and writing uncorrectable data in a memory area, which is included in each of the plurality of memory devices and the at least one ECC device and corresponds to the first address, when an error of the user data is not corrected based on the ECC data.

Operation method of memory module, operation method of memory controller, and operation method of memory system

An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.

Semiconductor device and electronic device including the same

An operation method of a memory device, having a plurality of memory cells, includes receiving a partial write command, which includes a partial write enable signal (PWE) and a plurality of mask signals, during a command/address input interval. A data strobe signal is received through a data strobe line after receiving the partial write command Data is received through a plurality of data lines in synchronization with the data strobe signal during a data input interval. A part of the data is stored in the plurality of memory cells based on the plurality of mask signals, in response to the partial write enable signal, during a data write interval.

Electronic device, operation method of host, operation method of memory module, and operation method of memory device

A semiconductor device including a memory device which has improved reliability is provided. The semiconductor device comprises at least one data pin configured to transfer a data signal, at least one command address pin configured to transfer a command and an address, at least one serial pin configured to transfer a serial data signal, and processing circuitry connected to the at least one data pin and the at least one serial pin. The processing circuitry is configured to receive the data signal from outside through the at least one data pin, and the processing circuitry is configured to output the serial data signal through the at least one serial pin in response to the received data signal.

Semiconductor device and electronic device with serial, data transfer mechanism

A memory module includes a memory device configured to receive a first refresh command from a host, and perform a refresh operation in response to the first refresh command during a refresh time, and a computing unit configured to detect the first refresh command provided from the host to the memory device, and write a first error pattern at a first address of the memory device during the refresh time.

Memory module and operating method

A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.

Method for accessing semiconductor memory module

A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

Memory device and memory module including same

An oscillator for high-frequency signal generation is disclosed. Provided according to the present invention is an oscillator for high-frequency signal generation comprising: a first transistor comprising a first collector for receiving a power supply voltage from a load, a first base connected to a ground, and a first emitter connected to the first base; and a second transistor comprising a second collector for receiving a power supply voltage from the load, a second base connected to a ground, and a second emitter connected to the second base, the oscillator having a common-base cross-coupled structure in which the first collector and the second emitter are cross-coupled and the second collector and the first emitter are cross-coupled.

Oscillator for high-frequency signal generation

A compatible circuit and method for 4- and 5-pole earphones and a portable device are disclosed. The compatible circuit and method alter the path of audio signals, using switches, according to control signals, so that the 4-pole earphone can be used in a portable device designed primarily for a 5-pole earphone. The apparatus and method include determining the type of earphone, altering the audio signal path according to the type of earphone, and transmitting the audio signal to the earphone.

Compatible circuit and method for 4- and 5-pole earphones and portable device using the same

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Seoul, South Korea

Nam Hyung Kim