International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Nam Huu Pham

Bhyrav M Mutnury

Moises Cases

Erdem Matoglu

Pravin S Patel

Lloyd Andre Walls

Bradley Donald Herrman

Daniel Mark Dreps

Daniel N De Araujo

Terence K Rodrigues

Jose A Hejase

Nanju Na

Justin Potok Bandholz

Pavel Roy Paladhi

Caleb James Wesley

Kent Barclay Howieson

Prasanna Jayaraman

Christopher Collier West

James Douglas Jordan

Robert J Christopher

Rubina Firdaus Ahmed

Michael D Hasse

Bradley D Herman

Thomas D Pahel

John Michael Borkenhagen

Saravanan Sethuraman

Wiren Dale Becker

Sungjun Chun

Bruce James Wilkie

James Joseph Parsonese

Anil Bindu Lingambudi

Robert Russell Williams

Shiva R Dasari

Byron Lee Krauter

Jason R Eagle

Tae Hong Kim

Francesco Preda

Keenan Wynn Franz

Junyan Tang

Vinh B Lu

Sang Y Lee

Nathan Lee Dunfee

David LeRoy Guertin

Jose A Hajase

Terence Rodrigues, Jr

Menas Roumbakis

Bhyrav Murthy Mutnury

An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.

Dense via pitch interconnect to increase wiring density

A computer controls voltage supply for a system that includes a plurality of active cables. The computer determines that a first voltage source included in a first cable has failed to provide a required amount of voltage to the first cable. The computer switches the first cable to a second voltage source included in a second cable. The second voltage source provides voltage to the first cable.

Redundant voltage delivery with active cables

A computer uses an active cable architecture to control communications. The computer sends a first set of instructions for completion of an activity to a first micro-controller of an active communication cable. The computer determines that at least one transceiver of an active cable is to receive a set of signals from the first micro-controller. The computer forms a communication connection between the first micro-controller and the at least one transceiver. The computer sends a second set of instructions to the at least one transceiver, wherein the second set of instructions instruct the at least one transceiver to complete at least a portion of the activity.

Architecture with micro-controller and high-speed active cables

An apparatus, multi-layer semiconductor substrate and system for testing a high-speed signal through a printed circuit board is provided. Embodiment of the present invention provides an apparatus comprises a multi-layer substrate, one or more transmission lines disposed within the multi-layer substrate, one or more connectors attached to the multi-layer substrate for connecting one or more test cards, a lid, comprising one or more cutouts for the one or more connectors, a clamp for compressing the multi-layer substrate against the lid, and one or more high-speed connectors attached to the one or more test cards, respectively.

High speed chip substrate test fixture

Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator.

Noise modulation for on-chip noise measurement

A frequency band splitter is disclosed. The frequency band splitter includes a first, a second, and a third waveguides. A first narrow rectangular waveguide is utilized to connect the first waveguide to second waveguide. The first narrow rectangular waveguide has a first width to allow signals of a frequency band centered around a first frequency to be transmitted from the first waveguide to the second waveguide. A second narrow rectangular waveguide is utilized to connect the first waveguide to the third waveguide. The second narrow rectangular waveguide has a second width, which is different from the first width, to allow signals of a frequency band centered around a second frequency to be transmitted from the first waveguide to the third waveguide.

Method for performing frequency band splitting

A memory system is deigned for impedance matching using a network of resistors that are tuned to reduce reflections on a shared bus. Any deviation from the matched state causes a mismatch and results in reflections on the bus. Overall signal reflections are reduced by balancing the back reflections occurring at a connector junction coupled to a pair of resistors and the back reflections occurring at the input of the DIMMs. This balance or tradeoff is achieved by changing the resistance value of the resistor pair to reduce the overall back reflections in the memory system.

Impedance matching system for DDR memory

In a particular embodiment, a method of manufacturing a printed circuit board ('PCB') with reduced dielectric loss includes fabricating conductive traces disposed upon layers of dielectric material; and fabricating the layers of dielectric material, including core layers and prepreg layers, with one or more of the layers of dielectric material including pockets of air that reduce an overall relative dielectric constant of the PCB. In the particular embodiment, the conductive traces are disposed upon layers of the dielectric material orthogonally with respect to one another and the pockets of air are aligned at an angle of 45 degrees with respect to the conductive traces.

Manufacturing a printed circuit board with reduced dielectric loss

A printed circuit board is disclosed. The printed circuit board includes a first signal transmission layer, a via and a second signal transmission layer. The via connects the first signal transmission layer to the second signal transmission layer. The via includes a first region made of a first dielectric material having a first dielectric constant, and a second region made of a second dielectric material having a second dielectric constant lower than the first dielectric constant. The via allows AC Component of an electromagnetic signal to be transmitted from the first signal transmission layer to the second signal transmission layer while blocking any DC component of the electromagnetic signal.

Printed circuit board having DC blocking dielectric waveguide vias

An improved electrical connector for connecting bus lines to a card such as a memory card or media card, including a multi-level connector comprising a latching device having a plurality of insertable latch positions that advantageously allows for selectively connecting or isolating an electrical path to an adjoining connector. The connectors of unpopulated DIMM slots are disconnected from the network along with the traces that would normally form a stub with associated undesirable signal reflections that would otherwise disturb the signal transmitted to the receiving end if not properly terminated. The contacts of the edge connector itself are used as a means to selectively connect or disconnect adjacent/downstream cards in a serially cascaded architecture. The burden of the stubs due to unpopulated card slots and the need to place one card at the far end of the network are thus eliminated.

Multi-level connector and use thereof that mitigates data signaling reflections

Apparatus and methods for identifying a signal on a printed circuit board (PCB) under test, including an integrated circuit mounted on the PCB, the integrated circuit having a test signal generator that transmits a test signal to an output pin of the integrated circuit, with the output pin connected to a test point on the PCB; the integrated circuit also having signal identification logic that inserts into the test signal, an identifier of the signal; a test probe in contact with the test point; and a signal-identifying controller that receives the test signal and the identifier from the test probe and displays, in dependence upon the identifier, the identity of the signal.

Identifying a signal on a printed circuit board under test

A circuit board includes layers, a pair of vias filled with a conductive material and extending through the layers, first and second pairs of conductive signal paths, and holes extending at least partially through the layers and located between the pair of vias. The first pair of conductive paths is connected to the pair of vias within a first layer; the second pair of conductive paths is connected to the pair of vias within a second layer. The pair of vias has a pair of via stubs defined between the second layer and a bottom layer. A differential signal is to be transmitted between the first and second pairs of conductive signal paths via the pair of vias. The holes have a lower dielectric constant than the layers to increase a resonant frequency of the pair of via stubs beyond the frequency of the differential signal.

Method for manufacturing circuit board having holes to increase resonant frequency of via stubs

Growing community of inventors

Round Rock, TX, United States of America

Nam Huu Pham