Google Inc.

Other

The State University of New York

Kdx Diagnostics, Inc.

Oncogenesis, Inc.

Nam Hoon Kim

Teckgyu Kang

Woon-Seong Kwon

Woon Seong Kwon

Yujeong Shim

Mikhail Popovich

Houle Gan

Scott Lee Kirkman

Kenneth R Shroyer

Luisa F Escobar-Hoyos

Xin Li

Calvin B Harley

Michael D West

Ryohei Urata

Jerry W Shay

Woodring E Wright

Shuai Jiang

Scott L Weinrich

Chenhao Nan

Qiong Wang

Christopher E Todd

Peter P Gombrich

Cheng Chung Yang

Sang K Yon

Jaesik Lee

A microelectronic system may include a microelectronic component having electrically conductive elements exposed at a first surface thereof, a socket mounted to a first surface of the microelectronic component and including a substrate embedded therein, one or more microelectronic elements each having active semiconductor devices therein and each having element contacts exposed at a front face thereof, and a plurality of socket pins mounted to and extending above the substrate, the socket pins being ground shielded coaxial socket pins. The one or more microelectronic elements may be disposed at least partially within a recess defined within the socket. The socket may have a land grid array comprising top surfaces of the plurality of the socket pins or electrically conductive pads mounted to corresponding ones of the socket pins, and the element contacts of the one or more microelectronic elements may be pressed into contact with the land grid array.

Socket to support high performance multi-die ASICs

A voltage regulator having a multiple of main stages and at least one accelerated voltage regulator (AVR) bridge is provided. The main stages may respond to low frequency current transients and provide DC output voltage regulation. The AVR bridges are switched much faster than the main stages and respond to high frequency current transients without regulating the DC output voltage. The AVR bridge frequency response range can overlap with the main stage frequency response range, and the lowest frequency to which the AVR bridges respond may be set lower than the highest frequency to which the main stages respond.

Trans-inductor voltage regulator for high bandwidth power delivery

The current disclosure provides methods for detecting and analyzing K17 expression in a bladder sample obtained from a subject. The current disclosure also pertains to methods and kits for identifying a mammalian subject with bladder cancer by detecting the expression of K17 in a sample. The present methods include both cell-based and cell-free methods for determining the level of keratin 17 in a sample obtained from the bladder of a subject.

Keratin 17 as a biomarker for bladder cancer

The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.

ASIC package with photonics and vertical power delivery

An integrated circuit package including a substrate configured to receive one or more high-bandwidth memory (HBM) stacks on the substrate, an interposer positioned on the substrate and configured to receive a logic die on the interposer, a plurality of interposer channels formed in the interposer and connecting the logic die to the one or more HBM stacks, and a plurality of substrate traces formed in the substrate and configured to interface the plurality of interposer channels to the one or more HBM stacks.

Integrated circuit package for high bandwidth memory

This disclosure relates to deep trench capacitors embedded in a package substrate on which an integrated circuit is mounted. In some aspects, a chip package includes an integrated circuit die that has a power distribution circuit for one or more circuits of the integrated circuit. The chip package also includes a substrate different from the integrated circuit and having a first surface on which the integrated circuit die is mounted and a second surface opposite the first surface. The substrate includes one or more cavities formed in at least one of the first surface or the second surface. The chip package also includes one or more deep trench capacitors disposed in at least one of the one or more cavities. Each deep trench capacitor is connected to the power distribution circuit by conductors.

Deep trench capacitors embedded in package substrate

A mass transportation system provides an airborne passenger vehicle tethered to a host vehicle. The host vehicle traverses along a fixed route. The airborne passenger vehicle moves between a stowed position fixedly secured to the host vehicle and a deployed position in which the airborne passenger vehicle is flying above the host vehicle.

Tethered aircraft mass transportation

The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

Backside integrated voltage regulator for integrated circuits

A packaged assembly and a method of producing the packaged assembly is disclosed. The packaged assembly includes a redistribution layer (RDL), an integrated circuit (IC), one or more memory modules, and an interposer comprising a plurality of vias from a list of through-silicon-vias (TSVs), through-mold-via (TMVs), and plated-through-hold-via (PTHs). In some implementations, the IC is electrically and mechanically attached to a first side of the RDL. In some implementations, the one or more memory modules and the interposer are disposed on a second side of the RDL. The packaged assembly also includes a mold having a mold material encapsulating the IC, the one or more memory modules, the interposer, and the RDL to form the packaged assembly. In some implementations, the IC is electrically conductively connected an external circuit board via a series of electrical connections between the IC, the RDL, the vias, and the external circuit board.

Wafer level fan-out application specific integrated circuit bridge memory stack

A processor assembly and a system including a processor assembly are disclosed. The processor assembly includes an interposer disposed on a substrate, an integrated circuit disposed on the interposer, a memory circuit disposed on the interposer and coupled to the integrated circuit, and a capacitor embedded in the interposer. The capacitor includes at least a first non-planar conductor structure and a second non-planar conductor structure separated by a non-planar dielectric structure. The capacitor includes a first capacitor terminal electrically coupling the first non-planar conductor structure to a first voltage terminal in the integrated circuit. The capacitor includes a second capacitor terminal electrically coupling the second non-planar conductor structure to a second voltage terminal in the integrated circuit. The capacitor includes an oxide layer electrically isolating the capacitor from the interposer.

Massive deep trench capacitor die fill for high performance application specific integrated circuit (ASIC) applications

Systems and methods for detection of analytes by production of electrochemical species are provided. Some embodiments of this invention relate generally to carbon biosensors for detecting an analyte in a biological sample. More specifically, this invention relates generally to immunoassays for detection of analytes utilizing electroactive compounds, and more particularly, relates to diagnostic assays based on signals from electroactive chemical undergoing redox cycling on electrosensor consisting of carbon, to detect analytes wherein a precomplex mixture is formed and a multi-step, or single-step, assay is performed, resulting in greater signal.

System, method and kit for detection of analytes by production of electrochemical species

Integrated component packages and methods of assembling integrated component packages are provided. The integrated component package can comprise a bump pitch relaxing layer. A high-bandwidth memory component directly mechanically coupled to the bump pitch relaxing layer on a first side of the bump pitch relaxing layer via a first set of bump bond connections. The high-bandwidth memory component directly electrically coupled to the bump pitch relaxing layer on the first side of the bump pitch relaxing layer via the first set of bump bond connections. The bump pitch relaxing layer mechanically coupled to a first side of a substrate via second set of bump bond connections. The high-bandwidth memory component electrically coupled to the substrate via the bump-pitch relaxing layer and the second set of bump bond connections, and a bump pitch of the second set of bump bond connections is larger than the first set of bump bond connections.

Growing community of inventors

Mountain View, CA, United States of America

Nam Hoon Kim