Exar Corporation

Integrated Device Technology, Inc.

Other

Nvidia Corporation

Nam Duc Nguyen

Michael Shannon McCorquodale

Scott Michael Pernia

Sundus Kubba

Justin O'Day

Ralph Beaudouin

Min Ming Tarng

Ismail H Ozguc

A decision feedback equalizer system is disclosed. The decision feedback equalizer system includes a current summer core that in current mode, removes inter-symbol interference from a signal, and, a CMOS latch component, that is coupled to the current summer core, that receives a current mode signal and outputs a CMOS compatible signal. The components of the decision feedback equalizer system are controlled by a single clock.

Decision feedback equalizer using current mode processing with CMOS compatible output level

Exemplary embodiments of the invention provide a reference signal generator having a controlled quality ('Q') factor. An exemplary apparatus to generate a harmonic reference signal includes a reference resonator, such as an LC-tank, which generates a first reference signal having a resonant frequency, and a plurality of reactance modules couplable to the reference resonator. Each reactance module comprises one or more reactance unit cells, and each reactance unit cell comprises a reactance element coupled in series to a switching element. In exemplary embodiments, the reactance element is a capacitor having a predetermined unit of capacitance, and the switching element is a transistor having a predetermined resistance when in an off state. The ratio of capacitance to resistance is substantially constant for all reactance modules of the plurality of reactance modules.

Clock, frequency reference, and other reference signal generator with a controlled quality factor

Exemplary embodiments of the invention provide a reference signal generator, system and method. An exemplary apparatus to generate a harmonic reference signal includes a reference resonator, such as an LC-tank, a control voltage generator adapted to provide a temperature-dependent control voltage; and a plurality of variable reactance modules. The reference resonator generates a first reference signal having a resonant frequency, and each reactance module is adapted to modify a corresponding reactance in response to the control voltage to maintain the resonant frequency substantially constant or within a predetermined variance over a predetermined temperature range. A frequency controller may also be included to maintain substantially constant a magnitude of a peak amplitude of the first reference signal and maintains substantially constant a common mode voltage level of the reference resonator.

Control voltage generator for a clock, frequency reference, and other reference signal generator

A sub-bandgap reference voltage generator, generates a pair of variable voltages one having a positive temperature coefficient and one having a negative voltage coefficient. The pair of voltages are added to generate an output voltage whose value and temperature may be varied. To achieve this, a first voltage having a positive temperature coefficient is multiplied by a first ratio defined by first and second resistive values to generate a second voltage. A third voltage having a negative temperature coefficient is multiplied by a second ratio defined by third and fourth resistive values to generate a fourth voltage. The second and fourth voltages are added together to generate the output voltage of the sub-bandgap voltage generator.

Variable sub-bandgap reference voltage generator

A phase detector is adapted to receive first and second signals and generate third and fourth signals representative of the difference between the phases of the first and second signals. The phase detector assert the third signal in response to the assertion of the first signal and unasserts the third signal in response to the assertion of the second signal. The phase detector asserts the fourth signal in response to the assertion of the third signal and unasserts the fourth signal in response to unassertion of the first signal. The phase detector may include combinatorial logic gates, thereby to generate the third and fourth signals in response to logic levels of the first and second signals. The phase detector may include sequential logic gates, thereby to generate the third and fourth signals in response to transitions of the first and second signals.

Phase detector for RZ

The input stage of an operational amplifier includes at least four signal-receiving stages adapted to receive four primary input signals. If the voltage level associated with any of the input signal changes, at least one transistor in each of the at least four signal-receiving stages conducts more current and at least one transistor in each of these stages conducts less current. The four signal-receiving stages collectively generate at least four intermediate signals that are delivered to the output stage of the differential amplifier, which in response, generates a pair of differential output signals. Two of the input signals are derived from the pair of differential output signals and are fed back to control the amplifier.

Differential operational amplifier

A flip-flop is configured to operate either in a double data-rate mode or a normal mode. When configured to operate in the double data-rate mode, the flip-flop outputs data on both edges of the applied clock. When configured to operate in the normal mode, the flip-flop outputs data on either the rising or falling edges of the applied clock. In the double data-rate mode, when a first latch disposed in the flip-flop operates in a sampling mode, the second latch disposed in the flip-flop operates in a holding mode to supply the output data, and when the second latch operates in the sampling mode, the first latch operates in the holding mode to supply the output data. Accordingly, with each of the rising or falling edge of the clock, one of the latches supplies an output data.

Dual data rate flip-flop

The input stage of an operational amplifier includes at least four signal-receiving stages adapted to receive four input signals. If the voltage level associated with any of the input signal changes, at least one transistor in each of the at least four signal-receiving stages conducts more current and at least one transistor in each of these stages conducts less current. The four signal-receiving stages collectively generate four intermediate signals that are delivered to the output stage of the differential amplifier, which in response, generates a pair of differential output signals. Two of the input signals are derived from the pair of differential output signals and are fed back to the input stage of the amplifier.

Differential amplifier

A universal portable minidisk drive system adopts the (1) universal head (2) laser pin (3) timing/coordinate clock track to have the long-time, continue-playing for all the different disk media such as optic disk, magnetic disk or magnetopic disk. The universal head enables the universal disk to read/write all the different disk that the portable computer only needs to have one kind of disk drive. The laser pin pushes the track density to the extreme limit that the minidisk can store a large amount data. The timing/coordinate clock track introduces the (track, sector) coordinate system to the disk that the access/recover time is reduced. The disk drive can play continuously in the vibrant environment.

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San Jose, CA, United States of America

Nam Duc Nguyen