Advanced Micro Devices Corporation

Nallepilli S Ramesh

Subramanian Narasimhan

Anders Erikson

Suresh Cheemalavagu

A method of sampling marks on a transmission line and adjusting their peak amplitude to compensate for attenuation of signal strength on the line and of 'voltage addition' caused by multiple terminals transmitting on the line. For networks meeting the CCITT I-Series Recommendation, two B-channels and a D-channel are transmitted in frames over the line; the B-channel forming the best basis for threshold adaptation, the D-channel the next best basis and the F-bit preceeding each frame used in the absence of either B- or D-channel signals. Accordingly, a B-bit mark sample is taken if possible, otherwise a D-bit mark sample; or if neither is present an F-bit mark sample; the adaptive threshold preferably being set at 55% of the peak value of the sample. The method is readily implemented as a 'state machine' and consequently can be constructed from a programmable logic array.

Adaptive threshold sampling controller

Method and apparatus for rapid, low-jitter acquisition of a clock signal at a serial communication port. In the absence of communication over the port, and during clock acquisition, a free-running clock is generated for local communication. Following clock acquisition by a circuit which performs coarse phase adjustments, a simple logic network generates refined phase adjustment signals which drive a variable, nominal divide-by-32, counter so that the clock generated thereby is smoothly brought into synchronization with the acquired clock in one bit increments. In a typical application, at most 48 bit periods at the port are required to synchronize the clock, with a clock phase jitter of less than 1.1%.

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Nallepilli S Ramesh