S3 Incorporated, Inc.

Nalini Ranjan

Sarathy Sribhashyam

Henry Yang

Xiaoyi Guo

David L Hoff

Yi-Hen Wei

Gregg Bardel

Saleh Abdel-Hafeez

A word line block, a data block and at least one memory cell form a memory architecture and impose no special timing requirements to handle the synchronization of the outputs of the word line block with the data block. Further, the word line block contains a transmitting transistor and the data block contains a functionally similar transmitting transistor. These transmitting transistors responsive to a write enable signal and a clock signal synchronize a selection signal supplied to the memory cell when data is also supplied to the memory cell. Furthermore, a place in route tool can automatically place and route the word line block, the data block and the at least one memory cell based on chip requirements. Also, with the clock signal proximate the output of the word line block and data block, the place and route tool is able to automatically place and route the blocks and the at least one memory cell to compensate for any calculated interconnection delays. Moreover, since the word line block, the data block, and the at least one memory cell are separate blocks, flexibility is provided in the placement of the blocks as each block requires a reduced amount of layout space as compared to all three blocks together. Also provided is a process using synthesis method for creating a digital electronic circuit with the memory architecture including the word line block, the data block, and the at least one memory cell.

Skew-independent memory architecture

A single rail domino logic circuit using a four-phase clocking scheme. A stacked PMOS pair provides a quarter clock cycle precharge time. The quarter clock cycle precharge time allows for placement of an additional inverter in the output signal path to form both an output signal and a complement of the output signal for use in subsequent logic stages.

Single rail domino logic for four-phase clocking scheme

The present invention provides a buffer for coupling circuitry operating at a low voltage to circuitry operating a high voltage, and vice versa. The buffer outputs signals in a range between the low voltage and a ground voltage lower than the low voltage, and maintains appropriate bias of a semiconductor junction in the buffer using the high voltage. For example, the high voltage can be applied to the body of an output stage pull-up PFET of the buffer to maintain reverse bias between the body and drain of the PFET even when signals at the high voltage are placed on the drain of the PFET by other circuitry. Some embodiments of the present invention include a voltage translator to translate signals output from circuitry operating at the low voltage into a control signal at either the ground voltage or the high voltage. The high voltage of the control signal is beneficial for turning OFF an output stage transistor of the buffer even in the presence of signals at the high voltage on an output of the buffer. The roles of the low and high voltage can also be reversed, for example, by using a ground voltage higher than the high voltage.

Voltage tolerant buffer

The present invention provides improved output buffers for use on IC Chips. These output buffers incorporate a compensation circuit for compensating the performance characteristics of transistors included in the output buffers. The compensation circuit determines whether the output buffer is operating at a desired slew-rate. In response to this determination, the compensation circuit supplies a compensation voltage or voltages. The compensation voltages control a variable quantity of power delivered by a voltage controlled power source (VCPS). By increasing or reducing this power, the slew-rate of the output buffers are respectively increased or reduced. The compensation voltages maintain this slew-rate within narrow tolerances. This allows the improved output buffers of the present invention to meet very narrow input tolerances of circuitry coupled to receive signals from the IC Chip. The compensation circuit of the present invention is also beneficial for compensating various circuitry on an IC Chip, such as amplifier designs using constant current or power sources.

Output buffer circuit and method that compensate for operating

Improved conductive pads and conductive lines for use on integrated circuit chips include one or more conductive layers having a wider width than convention conductive lines for improved current and power carrying capacity. A layer of insulating and shock resistant is included over said layers of wider width, and additional pads can be formed on said layer of insulating and shock resistant material. Additional improved conductive pads are formed on the integrated circuit chip over a region containing a conductive line. The improved pads and conductive lines provide high power and current carrying capacity, and simultaneously allow for high pad density on an integrated circuit chip. Said pads and conductive lines can include a layer of metal which is electrically insulated using upper and lower layers of insulating material, with this layer of metal providing shock resistance particularly to such lower layer of insulating material.

High DC current stagger power/ground pad

An I/O interface includes latches, clocks, and conditioning circuits implemented in a custom physical layout to produce a reliable and flexible interface to high frequency busses running a plurality of protocols and signal specifications. Three clock trees are used to synchronize the buffering and conditioning of input/output signals before sending such signals to a pad or core. The clock trees are implemented via custom layouts to allow tight control of clock/strobe parameters (e.g., skew, duty cycle, rise/fall times). Two of the clock trees are local to the I/O interface and trigger a plurality of output latches configured on-the-fly to buffer output data signals from the core in asynchronous or synchronous mode. In the synchronous mode, a clock/strobe could be either edge-centered or window-strobe with respect to the data. The third clock tree distributes clock/strobes from an external source and is used to trigger a plurality of input latches configured on-the-fly to buffer input data from the pad in either a window-strobe mode or an edge-centered mode. The I/O interface also includes conditioning circuits that condition the I/O signals to be compliant with AGP/DDR protocols, as well as, full swing, reduced swing (SSTL), and TTL signal specifications.

AGP/DDR interfaces for full swing and reduced swing (SSTL) signals on an

A voltage level shift system transitions a voltage signal between two components and includes a first inverter, a signal pass subsystem, a pull-up transistor, a second inverter, and a third inverter. The first inverter is coupled to the signal pass subsystem. The signal pass subsystem is coupled to the pull-up transistor, the second inverter, and the third inverter. The signal pass subsystem includes a first passgate and a second passgate. When an input voltage transitions from a logic low to a logic high, the first inverter inverts the logic high input signal to a logic low and passes this signal through the passgate subsystem. The second inverter receives the logic low signal and immediately inverts it to transition the output signal from a low logic to a logic high. The logic high output signal, turns off the pull-up transistor. When the input signal transitions from a logic high to a logic low, the first inverter receives the signal and generates a logic low signal that passes through the passgate subsystem. The second inverter receives the logic low signal and immediately inverts it to transition the output signal from a logic high to a logic low. The logic low signal places the pull-up transistor in an on state to turn off the p-device in the circuit. A method for transitioning a voltage signal between two components is also disclosed.

Voltage level shift system and method

A universal input/output buffer uses all digital-type components, can be included on an integrated circuit chip and operates in a mixed voltage, multi-rail, power supply environment. The input/output buffer includes a multi-stage driver section and a sequencing section. Several types of sequencing techniques are used to control a plurality of driver stages and provide a combination of multiple firing schemes. In addition, other control techniques are employed such as full and partial feedback, sequential turn on/turn off of driver stages, and controlled introduction of a small amount of 'crow bar' current.

Mixed voltage, multi-rail, high drive, low noise, adjustable slew rate

An adder system includes at least one adder block subsystem. Each adder block subsystem includes a pair of input signal lines, an adder circuit block having a conditional sum-select and a conditional carry-select, a sum-high line, a sum-low line, a carry-high line, carry-low line, a sum selection switch, a carry selection switch, a carry forward line, and an output signal line. The input lines are individual bit lines that are paired together from the least significant bit to the most significant bit. Within the adder circuit block, pairs of the input bit lines are coupled to the conditional sum-select and the conditional carry-select. The conditional sum-select is coupled to the sum-high and sum-low lines and the conditional carry-select is coupled to the carry-high and carry-low line. The sum selection switch selectively couples the output signal line to the sum-high or the sum-low line. The carry selection switch selectively couples the carry-high or carry-low line to the carry forward line that is coupled to the next adder subsystem which is structured similarly. The carry signal of the adder system is determined through the conditional carry selects of the adder circuit blocks. Each conditional carry-select includes logic OR and logic AND subcircuits to which each of the pairs of input bit lines is respectively coupled. The outputs of the logic OR and logic AND subcircuits are coupled to one or more line multiplexes to selectively produce a logic high or logic low signal that serves as the individual carry bit signals for the carry signal. A method for an adder system is also disclosed.

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San Jose, CA, United States of America

Nalini Ranjan