Hitachi, Ltd.

Nakaba Sato

Hiroji Shibuya

Toshiaki Terao

Jun Kitahara

Toshio Kimura

Mika Teranishi

Kazushige Nagamatsu

Kazusige Nagamatsu

The present invention enables program codes to be shared among processors. To prevent the debug operation of one processorfrom affecting the debug operation of the other processors, when detecting a breakpoint during execution of a program code, a debuggeror a debugger stubcontrols the execution of the program code while exchanging breakpoint informationwith the other debuggersor the other debugger stubs. Furthermore, a circuitis created which prevents the program code being carelessly rewritten due to thermal runaway, a bug, and the like of a processor, and the protection setting by the protection logicin the circuitis released only in case the processoraccesses each of a plurality of registers fromtoin specified order.

Controlling program code execution shared among a plurality of processors

Even if each processor core uses the same logical address, a processing-target program corresponding to each processor core can be selected. A logical address of multiple address mapping tables is set to a same logical address in correspondence with an embedded OS program or a RAID management program, and a physical address is set to a different physical address in correspondence with the actual storage destination of an embedded OS program or a RAID management program. Each processor core, on start-up, uses a self address mapping table to execute address mapping processing with each processor core based on the same logical address, selects an embedded OS program or a RAID management program according to the physical address obtained in the address mapping processing, and executes processing according to the selected program.

Multi-core address mapping for selecting storage controller program

A storage system has a single processor that operates in a multitasking operating system environment. An operation time manager adjusts the balance between processing time proportions for interrupt processing and task processing requested of the storage system internally and externally so that those processing time proportions become within respective predetermined ranges.

System for monitoring time proportion for interrupt or task processing with restriction placed in subsequent monitoring time period when allowable time proportion is exceed

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Odawara, Japan

Nakaba Sato