Ps4 Luxco S.a.r.l.

Elpida Memory, Inc.

Nakaba Kaiwa

Yutaka Ikeda

Hiroki Fujisawa

Tetsuaki Okahiro

Yoshinori Matsui

A semiconductor device having a circuit that selectively adjusts an impedance of an output buffer. A calibration operation can be performed automatically without issuing a calibration command from a controller. Because a calibration operation to a memory is performed in response to an auto refresh command having been issued for a predetermined number of times, a periodic calibration operation can be secured, and a read operation or a write operation is not requested from a controller during a calibration operation. A start-up circuit activates the calibration circuit when a refresh counter indicates a predetermined value, and prohibits a refresh operation in response to the auto refresh command when the calibration circuit is activated. A temperature detecting circuit may be used to change the frequency of performing a calibration operation.

Semiconductor device having a memory and calibration circuit that adjusts output buffer impedance dependent upon auto-refresh commands

A semiconductor memory device includes a memory cell array section including a plurality of memory cell arrays, a peripheral circuit section, and an internal bus connecting the plurality of memory cell arrays and the peripheral circuit section. The peripheral circuit section includes external input/output buffers, and bus interface circuits. The bus interface circuits execute conversion between data inputted/outputted in parallel to/from the memory cell arrays through the internal bus and data inputted/outputted in serial through the plurality of external input/output buffers. The bus interface circuits are densely arranged between the internal bus and the input/output buffers, so that a width dof the area of the plurality of bus interface circuits being arranged is narrower than a width dof the area of the external input/output buffers being arranged and a bus width maximum value dof the internal bus.

Semiconductor memory device for high speed reading and writing

Semiconductor device having a memory and calibration circuit that selectively adjusts an impedance of an output buffer dependent upon refresh commands

A device, comprising an output terminal; an output circuit coupled to the output terminal and having an adjustable impedance; and an impedance adjustment circuit adjusting stepwise the adjustable impedance so as to head toward a first reference impedance. The impedance adjustment circuit changes the adjustable impedance by a first amount when the adjustable impedance is within a first range, and changes the adjustable impedance by a second amount when the adjustable impedance is out of the first range. The first amount is smaller than the second amount.

Semiconductor device

A semiconductor device includes a signal generating circuit that generates an impedance adjustment command signal which indicates at least one of initiation and termination of an impedance adjustment. The semiconductor device outputs an output signal in synchronism with the impedance adjustment command signal.

A device includes a first circuit and an adjustment circuit. The adjustment circuit performs an adjustment on impedance of the first circuit. The adjustment circuit discontinues the adjustment on impedance while the first circuit is in an activated state.

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Tokyo, Japan

Nakaba Kaiwa