Electronics and Telecommunications Research Institute

Intellectual Discovery Co., Ltd.

Nak Woong Eum

Seong Mo Park

Kyung Jin Byun

Suk Ho Lee

Young-Su Kwon

Jin Ho Han

Moo Kyoung Chung

Bon Tae Koo

Young Su Kwon

Jun Young Lee

Kyoung Seon Shin

Jae-Jin Lee

Jae Jin Lee

Kyung Su Kim

Hee-Bum Jung

Sang Heon Lee

Seunghyun Cho

Ig Kyun Kim

Woo Joo Lee

Seung Hyun Cho

Hyuk Joo Kim

Jong Dae Kim

Ki Hyuk Park

Sukho Lee

Hee Bum Jung

Hyun Mi Kim

Woojoo Lee

June Young Chang

Young-Seok Baek

Ju Hyun Lee

Myung Sin Kwark

Hyeong Uk Jang

Provided is a display device including a display panel, a power delivery network (PDN), an image controller, and a PDN controller. The display panel may include a plurality of sub-panels. The PDN may be controlled by a control signal, respectively deliver voltages determined by the control signal to the plurality of sub-panels, and generate state information for determining the control signal. The image controller may receive to store frame image data, determine a number of frames to be integrated according to a window size, and integrate the frame image data of frames in the determined number into one image to generate integrated image data. The PDN controller may generate the control signal and a size adjusting signal based on the state information and the integrated image data, provide the generated control signal to the PDN, and may provide the generated size adjusting signal to the image controller. The size adjusting signal may adjust the window size.

Display device including power delivery network controller and display power management method using the same

Display device including power delivery network controller for controlling reconfigurable power delivery network for reducing power comsumption and display power management method using the display device

Provided is a processor system including a first processor driven by a first driving voltage and a first driving clock, a second processor driven by a second driving voltage and a second driving clock and configured to perform an identical task to the first processor, and a defect detector configured to perform level synchronization or clock domain synchronization on a first output signal provided from the first processor and a second output signal provided from the second processor to compare the first and second output signals, wherein the first and second driving voltages are respectively provided from mutually independent power supply sources and the first and second driving clocks are respectively provided from mutually independent clock generators.

Processor system and fault detection method thereof

Provided is a cache memory. The cache memory includes a first to Nth level-1 caches configured to correspond to first to Nth cores, respectively, a level-2 sharing cache configured to be shared by the first to Nth level-1 caches, and a coherence controller configured to receive an address from each of the first to Nth cores and allocate at least a partial area in an area of the level-2 sharing cache to one of the first to Nth level-1 caches based on the received address.

Cache memory and operation method thereof

Provided is an encoding method of an image encoding device including predicting an intra mode for coding blocks of a minimum size for intra prediction to generate an intra pixel; and using the intra mode of the coding blocks of the minimum size to restore an intra mode of coding blocks of a larger size.

Encoding method of image encoding device

Provided is an operating method of a cache memory device includes receiving an address from an external device, reading an entry corresponding to at least a portion of the received address among a plurality of entries that are included in the cache memory, performing error detection on additional information that is included in the read entry, and performing a recovery operation on the entry based on a result of error detection and the additional information. The entry includes the additional information and a cache line corresponding to the additional information, and the additional information includes a tag, valid bit, and dirty bit that correspond to the cache line.

Cache memory device and operating method thereof

An electronic device configured to perform forensic analysis on a target device includes a data extractor, an emulator, and a user data converter. The data extractor obtains, from the target device, a source file of at least one of applications installed on the target device. The data extractor obtains, from the target device, user data generated according to the least one of the applications being executed in the target device. The emulator emulates an execution of a target application installed based on the obtained source file. The user data converter converts the obtained user data having a data structure according to a database scheme of the target device into converted user data having a data structure according to a database scheme of the emulator. The emulator emulates the execution of the target application such that the target application operates using the converted user data.

Electronic device performing emulation-based forensic analysis and method of performing forensic analysis using the same

An Ultra Low Voltage (ULV) digital circuit includes a logic circuit comprising a plurality of logic gates and a plurality of buffered interconnects for connecting between the plurality of logic gates, a temperature sensor configured to detect a temperature of the logic circuit, and a voltage controller configured to control a driving voltage provided to the logic circuit in order to reduce a power consumption of the logic circuit based on the detected temperature. Each of the plurality of logic gates and buffered interconnects reduces a signal delay as a temperature increases.

Ultra low voltage digital circuit and operation method thereof

Provided is a multi-core simulation method including allocating, to a working memory, a shared translation block cache commonly used for a plurality of core models, reading a first target instruction to be performed in a first core model, generating a first translation block corresponding to the first target instruction and provided with an instruction set used in a host processor, performing the first translation block in the first core model after the first translation block is stored in the shared translation block cache, reading a second target instruction to be performed in a second core model, searching the shared translation block cache for a translation block including same content as that of the second target instruction, and performing the first translation block in the second core model, when the first target instruction includes same content as that of the second target instruction.

Multi-core simulation system and method based on shared translation block cache

Provided is a method for a plurality of processing elements to filter a plurality of pixel blocks in a plurality of picture partitions for a single frame image. The method for filtering pixel blocks includes: checking the status of a second boundary pixel block adjacent to a picture partition boundary, the second boundary pixel block being one of a plurality of pixel blocks in a second picture partition and neighboring a first boundary pixel block in a first picture partition, the first boundary pixel block neighboring the picture partition boundary; selecting a filtering area for the first boundary pixel block based on the status of the second boundary pixel block; and filtering the filtering area for the first boundary pixel block.

Method and apparatus for filtering pixel blocks

An apparatus for processing a register window overflow and underflow includes register windows each configured to include local registers and incoming registers, dedicated internal memories configured to store contents of the local registers and the incoming registers for each word, dedicated data buses configured to connect the local registers and the incoming registers and the respective dedicated internal memories, a memory word counter configured to perform counting in order to determine whether or not there is a storage space of a word unit in the dedicated internal memories, and a logic block configured to control an operation of the dedicated data buses when one of a window overflow and a window underflow is generated based on the count value of the memory word counter.

Apparatus for processing register window overflow and underflow

Disclosed is a parallel intra prediction method for video data, including: dividing, by an intra prediction unit, pixels included in at least one prediction unit configuring a coding unit or a sub-coding unit so as to belong to any one of a reference pixel group and a prediction group; generating, by the intra prediction unit, reference sub blocks and prediction sub blocks, respectively, using reference pixels belonging to the reference pixel group and prediction pixels belonging to the prediction pixel group; performing, by the intra prediction unit, encoding processing on the reference sub blocks; and performing, by the intra prediction unit, encoding processing on the prediction sub blocks.

Parallel intra prediction method for video data

A motion vector extraction method includes: deciding on a search start position in an original video and performing a spiral motion search; and determining whether or not to perform a search in a sub-sampling video, during P picture search.

Motion vector extraction method and apparatus

Disclosed are a method and a device for processing an image by using image division capable of simultaneously minimizing deterioration of an image quality due to an error in a transmission line and further improving compression efficiency in performing compression and restoration of an image signal by using multiple processors. The method of processing an image by using image division according to an exemplary embodiment of the present disclosure includes dividing an image frame into multiple subblocks having a predetermined pixel size; constituting multiple macroblocks by sampling respective pixels positioned at an identical position within a predetermined number of subblocks; and constituting multiple slices by dividing the multiple macroblocks based on the positions of the sampled pixels within the subblock.

Method and device for image processing by image division

Disclosed is a motion estimation apparatus and method capable of reduce a memory bandwidth by accessing reference image data occupying the largest part of the memory bandwidth based on a result of motion estimation skip determination. The motion estimation apparatus includes a motion estimation skip determination unit, a sum absolute of absolute difference (SAD) processing unit and a multiplexer (MUX) unit. The motion estimation skip determination unit determines the presence of motion estimation skip by reading current image data and skip reference image data, and outputs a motion vector in a skip mode. The SAD processing unit calculates an SAD value by reading the current image data and reference image data and outputs a motion vector in a normal mode. The MUX unit outputs the motion vector in the skip mode or the motion vector in the normal mode as a final motion vector based on a skip flag signal.

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Daejeon, South Korea

Nak Woong Eum