Samsung Electronics Co., Ltd.

Nak-Woo Sung

Hyun-Su Choi

Yong-jae Choo

Hyun-su Choi

Hyoung-Yun Byun

A read only memory (ROM) cell, a method for programming a ROM cell, a method for forming a layout of a ROM cell, and a ROM device including ROM cells are disclosed. The ROM cell includes a gate connected to a word line, a drain (or a source) connected to a bit line, and a source (or a drain) connected to a ground voltage line, a first selection signal line or a second selection signal line, or having no connection with the first and second selection signal lines, wherein the ROM cell is programmed with data &ldquo;00&rdquo; by connecting the source (or the drain) to the ground voltage line, with data &ldquo;10&rdquo; by connecting the source (or the drain) to the first selection signal line, with data &ldquo;01&rdquo; by connecting the source (or the drain) to the second seletion signal line and data &ldquo;11&rdquo; by not connecting the source (or the drain) to any signal lines. The ROM cell can store two bits of data, and the ROM cell can decrease layout size since an additional circuit is not needed to decrease difference of parasitic capacitances between bit lines.

Read only memory(ROM) cell, program method of ROM cell, layout method of ROM cell, and ROM device comprising ROM cell

The device comprises km memory cell array blocks arranged in the form of a matrix, divided by x block selecting signals and y block selecting signals, and including a plurality of divided word lines arranged horizontally; a plurality of bit lines for each of the km memory cell array blocks arranged vertically; a plurality of main word lines for a plurality of bit lines for each of the km memory cell array blocks arranged horizontally; km of xy address word lines above or below the km memory cell array blocks; a decoder for decoding a corresponding x block selecting signal among x block selecting signals generated by decoding the x block selecting address and y block selecting signals generated by decoding the y block address to select corresponding m of xy address word lines and for being arranged for each of m memory cell array blocks arranged horizontally among the km memory cell array blocks; km of divided y address lines arranged vertically from the km of xy address word lines to the km memory cell array blocks; and word line driver for combining the plurality of the main word lines of each of the km memory cell array blocks and a signal of a corresponding xy address word line among the km of xy address word lines to select the plurality of the divided word lines.

Hierarchical word line scheme with decoded block selecting signals and layout method of the same

A sense amplifier enable signal generating circuit includes a dummy bit cell which is connected to a dummy word line and a dummy bit line and discharges the dummy bit line in response to a signal level of the dummy word line. The sense amplifier enable signal generating circuit further comprises a process tracking circuit which adjusts a signal level of the dummy word line in response to a signal level of the dummy bit line to adjust a discharge rate of the dummy bit line, and a sense amplifier control circuit that generates the sense amplifier enable signal responsive to the signal level of the dummy bit line. In further embodiments, the sense amplifier control circuit includes a control circuit that generates the sense amplifier enable signal responsive to an internal clock signal and a control signal. A process adjusting circuit is connected to the dummy bit line and generates the control signal responsive to a signal level on the dummy bit line and the internal clock signal.

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Seoul, South Korea

Nak-Woo Sung