Samsung Electronics Co., Ltd.

Nak-hee Seong

Tae-Hun Kim

Jae-hong Park

Seh-woong Jeong

Min-young Joe

Yong-sang Yu

Ji-woong Kim

Man-hwee Jo

Sang-hoon Lee

Jae-Hong Park

Kyoung-Mook Lim

Young-Jun Kwon

Gun-young Bae

Tae-Sun Kim

Hyeok-Man Kwon

Kyoung-mook Lim

Hyung-jun Im

Young-Doug Kim

Seon-Young Yeo

Seung-Hong Jeon

Young-duck Kim

According to an aspect of inventive concepts, there is provided a memory controller configured to control a memory device including a plurality of memory pages, the memory controller including an error correction code (ECC) region manager configured to manage the plurality of memory pages by dividing the plurality of memory pages into ECC enable regions and ECC disable regions, and an ECC engine configured to perform an ECC operation on data included in the ECC enable regions.

Memory controller, memory system and application processor comprising the memory controller

Provided is a system including a multi channel memory and an operating method for the same. The multi channel memory may include a respective set of memories, wherein each set may include one or more memories. The operating method includes receiving access requests including system addresses for a multi channel memory having 2channels, where n is a natural number greater than 0, allocating a first channel of the 2channels based on n+1 or more bits of a first address of the system addresses, and performing an access of a respective set of memory devices through the allocated first channel.

System including multi channel memory and operating method for the same

An arbiter, a system, and a method for generating a pseudo-grant signal in response to a request and receiving target information in response to the pseudo-grant signal. The pseudo-grant signal reduces or eliminates waiting time.

Arbiter, a system and a method for generating a pseudo-grant signal

A video decoder organizes and stores pixel lines of a reference picture into first and second memory devices. The video decoder then reads portions of a pixel block from the first and second memory devices and processes such a pixel block for generating a subsequent picture. By reading from the first and second memory device with time overlap, latency is minimized for faster video decoding.

Method and apparatus for decoding video data

Apparatus and method for dispatching a very long instruction word (VLIW) instruction having a variable length are provided. The apparatus for dispatching a VLIW instruction includes a packet buffer for storing at least one or more VLIW instructions, and a decoding unit configured to constitute a VLIW instruction to be currently executed among the VLIW instructions stored in the packet buffer and decode predetermined bits of each sub-instruction contained in the VLIW instruction. The apparatus dispatches a corresponding sub-instruction to an FU which corresponds to each sub-instruction, based on the results of decoding performed in the decoding unit, position information on the sub-instructions that are placed on the packet buffer, and position information on the sub-instructions that are placed in the current VLIW instruction. Sub-instructions can be effectively dispatched to corresponding FUs using simple decoding logic even in a case where the length of the VLIW instruction is not fixed.

Apparatus and method for dispatching very long instruction word having variable length

Growing community of inventors

Gwacheon-si, South Korea

Nak-hee Seong