Analog Devices International Unlimited Company

Analog Devices Global

Analog Devices Technology

Naiqian Ren

Roberto Sergio Matteo Maurino

Patrick Martin McGuinness

Robert A Bombara

John P Healy

Michael Hennessy

Venkata Aruna Srikanth Nittala

Claire Croke

Mary McCarthy

Michael Edward Bradley

Finbarr O'Leary

Mayur Anvekar

Nigel David Brooke

George R Spalding

Techniques to deliver a precision low noise reference voltage to a precision analog-to-digital converter without the need of a reference buffer or digital correction. In an example, a technique can use an integrated resistor divider and external capacitor to derive a low noise precision reference voltage either from the power supply of the ADC, or from an integrated reference source.

Continuous-time sigma delta analog-to-digital converter

Systems and methods that combine multiple techniques such as supervised learning, data analytics, measurement hardware modelling and scalable sensing hardware to quickly deliver a highly optimized and production ready solution to cover the condition-based maintenance requirements of a specific physical asset.

Condition-based maintenance techniques

A wide bandwidth ADC circuit that combines a resistive-input continuous-time sigma-delta ADC circuit with a second ADC circuit having a switched capacitor input. The combination of these two ADC circuits can achieve an easy-to-drive, alias free, wide bandwidth ADC that has excellent DC precision.

Wide bandwidth ADC with inherent anti-aliasing and high DC precision

An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit including a serial data input, a serial data output, a serial clock input to receive a serial clock signal, and a master clock input to receive a master clock signal; a digital isolator circuit including outputs coupled to the serial clock input and serial data input of the sigma-delta ADC circuit, and an input coupled to the serial data output of the sigma-delta ADC circuit; an oscillator circuit unconnected to the digital isolator circuit and configured to generate the master clock signal asynchronous to the serial clock input signal; and wherein the sigma-delta ADC circuit generates an ADC sampling clock using the master clock.

Serial interface for oversampled and non-oversampled ADCs

This disclosure describes techniques to perform analog signal conditioning (including filtering and amplification) and analog-to-digital conversion (ADC) on a System-in-package (SIP) assembly technology. In particular, the disclosure combines a programmable gain amplifier (PGA), one or more filter circuits, and an ADC circuit onto the same SIP. These devices are coupled together on the SIP using high-accuracy and precise integrated-passive components. The SIP receives an analog signal, amplifies the analog signal with the PGA on the SIP, filters the amplified analog signal with the filter circuit(s) on the SIP, and then performs analog-to-digital conversion on the filtered amplified analog signal with the ADC circuit on the SIP. The SIP can be configured for various applications based on a variety of inputs and control mechanisms.

Data acquisition system-in-package

This disclosure describes techniques to perform analog signal conditioning (including filtering and amplification) and analog-to-digital conversion (ADC) on a System-in-package (SIP) assembly technology. In particular, the disclosure combines a programmable gain amplifier (PGA), one or more filter circuits, and an ADC circuit onto the same SIP. These devices are coupled together on the SIP using high-accuracy and precise integrated-passive components. The SIP receives an analog signal, amplifies the analog signal with the PGA on the SIP, filters the amplified analog signal with the filter circuit(s) on the SIP, and then performs analog-to-digital conversion on the filtered amplified analog signal with the ADC circuit on the SIP, The SIP can be configured for various applications based on a variety of inputs and control mechanisms.

Techniques for synchronization between multiple sampling circuits using a single pin interface to control an output data rate are described. The frequency or rate of a signal on this pin can be automatically determined and used to accomplish the required output data rate. Also described are techniques for using a single pin interface that can allow a sampling device to operate either in a master mode that can generate data strobes, or in a slave mode that can receive a convert start signal. Also described are techniques for controlling bandwidth and throughput for individual channels in a multi-channel device using a single pin interface. For example, using various techniques of this disclosure, integer multiple rate control for other channels can be provided thereby providing varying ODR for different channels, which can also control the bandwidth of interest.

Circuits, systems, and methods for synchronization of sampling and sample rate setting

A ping pong comparator voltage monitoring circuit which includes first and second comparators having inputs connected to a voltage Vin to be monitored, and second inputs connected to first and second nodes, respectively. A multiplexer alternately couples the first and second comparator outputs to an output in response to a periodic control signal. A ground-referenced voltage Vrefis provided at a third node and a voltage Vrefreferenced to Vrefis at a fourth node. A hysteresis hystis switchably connected between the third and first nodes, and a hysteresis hystis switchably connected between the fourth and second nodes. Hystand hystare switched in when the mux output toggles due to a rising Vin, and are switched out when the mux output toggles due to a falling Vin.

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Limerick, Ireland

Naiqian Ren