International Business Machines Corporation

Globalfoundries Inc.

Advanced Micro Devices Corporation

King Abdulaziz City for Science and Technology

Infineon Technologies Ag

Freescale Semiconductor,inc.

Sematech, Inc.

Naim Moumen

Michael Patrick Chudzik

Rashmi Jha

Theodore Gerard Van Kessel

Yves Corfield Martin

Siddarth A Krishnan

Robert L Sandstrom

Vijay Narayanan

Vamsi Krishna Paruchuri

Dae-Gyu Park

Keith Kwong Hon Wong

Wesley Charles Natzle

Hussam Khonkar

Steven J Holmes

Toshiharu Furukawa

Charles W Koburger, Iii

Supratik Guha

Renee Tong Mo

Unoh Kwon

Huiming Bu

Jochen C Beintner

William K Henson

Porshia Shane Wrschka

Alhassan Badahdah

Ayman Alabduljabbar

Abdullah I Alboiez

Yaseen G Alharbi

Ruilong Xie

Chanro Park

Michael A Gaynes

Hoon Sik Kim

Herbert Lei Ho

Martin Michael Frank

Richard Stephan Wise

Ravikumar Ramachandran

Eduard Albert Cartier

Brent A Wacaser

Hongwen Yan

Ricardo Alves Donaton

Yujun Li

Peter Daniel Kirchner

Dhirendra Patel

Mark J Hurley

Ying H Tsang

Wei He

Devendra K Sadana

Bruce Bennett Doris

Jeffrey P Gambino

Ghavam G Shahidi

Stephen W Bedell

Theodorus E Standaert

Ying Di Zhang

James William Adkisson

Thomas W Dyer

Steven J Bentley

Michael P Belyansky

Kathryn Turner Schonenberg

William James Taylor, Jr

Xi Li

Chienfan Yu

Muhammad Mustafa Hussain

Michael Abramovich Gribelyuk

James Kenyon Schaeffer, Iii

Andreas Knorr

Charlotte DeWan Adams

Byoung Hun Lee

Andreas Kerber

Rick J Carter

Bernd E Kastenmeier

Gabriel Gebara

Bernd Ernst Eduard Kastenmeier

Ed Labelle

Sidi Lanee

Barry Sassman

Raj Jammy

Babar A Kanh

Charles Iii Koburger

Techniques for cooling concentrating solar collector systems are provided. In one aspect, an apparatus for cooling a photovoltaic cell includes a heat exchanger having a metal plate with a bend therein that positions a first surface of the metal plate at an angle of from about 100 degrees to about 150 degrees relative to a second surface of the metal plate, and a plurality of fins attached to a side of the metal plate opposite the first surface and the second surface; a vapor chamber extending along the first surface and the second surface of the metal plate, crossing the bend; and a cladding material between the vapor chamber and the heat exchanger, wherein the cladding material is configured to thermally couple the vapor chamber to the heat exchanger. A photovoltaic system and method for operating a photovoltaic system are also provided.

Cooling system for high performance solar concentrators

Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.

Changing effective work function using ion implantation during dual work function metal gate integration

One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, performing an epitaxial deposition process to form an epi semiconductor material on the active region in the source/drain region of the device, performing an etching process on the epi semiconductor material to remove a portion of the epi semiconductor material so as to define at least one epi recess in the epi semiconductor material, forming a metal silicide layer on the upper surface of the epi semiconductor material and in the at least one epi recess in the epi semiconductor material, and forming a conductive structure that is conductively coupled to the metal silicide layer.

Methods of increasing silicide to epi contact areas and the resulting devices

A device for dissipating heat from a photovoltaic cell is disclosed. A first thermally conductive layer receives heat from the photovoltaic cell and reduces a density of the received heat. A second thermally conductive layer conducts heat from the first thermally conductive layer to a surrounding environment. An electrically isolating layer thermally couples the first thermally conductive layer and the second thermally conductive layer.

Thermal receiver for high power solar concentrators and method of assembly

Techniques for providing high-capacity, re-workable connections in concentrated photovoltaic devices are provided. In one aspect, a lead frame package for a photovoltaic device is provided that includes a beam shield; and one or more lead frame connectors affixed to the beam shield, wherein the lead frame connectors are configured to provide connection to the photovoltaic device when the photovoltaic device is assembled to the lead frame package. A photovoltaic apparatus is also provided that includes a lead frame package assembled to a photovoltaic device. The lead frame package includes a beam shield and one or more lead frame connectors affixed to the beam shield, wherein the lead frame connectors are configured to provide connection to the photovoltaic device.

Lead frame package for solar concentrators

Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.

High-K/metal gate stack using capping layer methods, IC and related transistors

One illustrative method disclosed herein includes, among other things, performing at least one recess etching process such that a first portion of a high-k oxide gate insulation layer and a first portion of a metal oxide layer is positioned entirely within a first gate cavity and a second portion of the high-k oxide gate insulation layer, a conformal patterned masking layer and a second portion of the metal oxide layer is positioned entirely within a second gate cavity, performing at least one heating process to form a composite metal-high-k oxide alloy gate insulation layer in the first gate cavity, while preventing metal from the metal oxide material from being driven into the second portion of the high-k oxide gate insulation layer in the second gate cavity during the at least one heating process, and forming gate electrode structures in the gate cavities.

Methods of forming transistor devices with different threshold voltages and the resulting products

A method for fabricating a CMOS device includes the following steps. A wafer is provided. STI is used to form at least one active area in the wafer. A silicon oxide layer is deposited onto the wafer covering the active area. A first high-k material is deposited onto the silicon oxide layer. Portions of the silicon oxide layer and the first high-k material are selectively removed, such that the silicon oxide layer and the first high-k material remain over one or more first regions of the active area and are removed from over one or more second regions of the active area. A second high-k material is deposited onto the first high-k material over the one or more first regions of the active area and onto a surface of the wafer in the one or more second regions of the active area. A CMOS device is also provided.

Techniques for the fabrication of thick gate dielectric

Electrical contact to the front side of a photovoltaic cell is provided by an array of conductive through-substrate vias, and optionally, an array of conductive blocks located on the front side of the photovoltaic cell. A dielectric liner provides electrical isolation of each conductive through-substrate via from the semiconductor material of the photovoltaic cell. A dielectric layer on the backside of the photovoltaic cell is patterned to cover a contiguous region including all of the conductive through-substrate vias, while exposing a portion of the backside of the photovoltaic cell. A conductive material layer is deposited on the back surface of the photovoltaic cell, and is patterned to form a first conductive wiring structure that electrically connects the conductive through-substrate vias and a second conductive wiring structure that provides electrical connection to the backside of the photovoltaic cell.

Grid-line-free contact for a photovoltaic cell

Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.

High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof

A semiconductor structure. The structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a gate dielectric region, and (iv) a gate electrode region, (v) a plurality of interconnect layers on the gate electrode region, and (vi) first and second spaces. The gate dielectric region is disposed between and in direct physical contact with the channel region and the gate electrode region. The gate electrode region is disposed between and in direct physical contact with the gate dielectric region and the interconnect layers. The first and second spaces are in direct physical contact with the gate electrode region. The first space is disposed between the first source/drain region and the gate electrode region. The second space is disposed between the second source/drain region and the gate electrode region.

Semiconductor transistors having high-K gate dielectric layers, metal gate electrode regions, and low fringing capacitances

Growing community of inventors

Walden, NY, United States of America

Naim Moumen