Ciena Corporation

Nortel Networks Corporation

Rockstar Consortium US LP

Naim Ben-Hamida

Sadok Aouini

Mahdi Parvizi

Mohammad Honarparvar

Soheyl Ziabakhsh Shalmani

Christopher Kurowski

Lukas Jakober

Yuriy Greshishchev

Jerry Yee-Tung Lam

Ahmad Abdo

Shahab Oveis Gharan

Timothy James Creasy

Douglas Stuart McPherson

Robert G Gibbins

Matthew Mikkelsen

Tingjun Wen

Jacob Pike

Kim Bryon Roberts

Calvin Plett

Hazem Beshara

Bilal Riaz

Junxian Weng

Yalmez M A Yazaw

Anna Sakharova

James St Harley

Tom M Luk

Gordon W Roberts

David V Plant

Andrew McCarthy

Manoj Verghese

Mouna Safi-Harab

Ahmed Mustafa

Ian Roberts

Nahla Abouelkheir

Euhan Chong

David Berton

Yalmez Yazaw

Harvey Mah

Youssef Karmous

Chris Kurowski

David Patel

Luhua Xu

Nicolás Abadía Calvo

Ahmed Emara

Lukas Jakpber

Douglas Mcpherson

Sadok Aouinin

Aspects of the subject disclosure may include, for example, a multiphase clock generator having a plurality of digital phase interpolators each configured to create a generated clock signal according to an applied digital code, wherein a first digital code applied to a first digital phase interpolator and a second digital code applied to a second digital phase interpolator are chosen in a less precise range such that a first generated clock signal output by the first digital phase interpolator is as close to an ideal phase separation from a second generated clock signal output by the second digital phase interpolator, and wherein additional codes are applied to other digital phase interpolators in a more precise range to create generated clock signals having a deviation from an ideal separation from the first generated clock signal or the second generated clock signal that is less than a linear resolution of the applied digital code. Other embodiments are disclosed.

Multiphase clock generator

A transceiver includes a first transmit (Tx) component configured to connect to a second receive (Rx) component in a second transceiver; a first Rx component configured to connect to a second Tx component in the second transceiver; a single Phase-Locked Loop (PLL) circuit connected to both the first Tx component and the first Rx component; and a control circuit configured to continuously calibrate a first Look-Up Table (LUT) configured to feed operating codes to a first phase rotator connected to an output of the single PLL circuit and to one of the first Tx component and the first Rx component. In an embodiment, the control circuit is further configured to continuously calibrate a second LUT configured to feed operating codes to a second phase rotator connected to an output of a single PLL circuit in the second transceiver.

Reducing non-linearities of a phase rotator

Described herein are apparatus and methods for digitally enhancing digital-to-analog converter (DAC) resolution. A digitally enhanced DAC includes a decoder circuit configured to convert a N-bit input data to at least N code bits, a digital enhancement circuit configured to logically operate on a least significant bit (LSB) of the N-bit data, and a switching network including at least N DAC unit elements, where a least significant DAC unit element is controlled by the digital enhancement circuit to output a factored nominal current or voltage when a logical operation outputs a defined logic level for the LSB and to output a nominal current or voltage absent output of the defined logic level and a remaining DAC unit elements are controlled by a remaining code bits of the at least N code bits. This provides a N+1 bit resolution for the DAC without increasing the at least N DAC unit elements.

Digitally enhanced digital-to-analog converter resolution

Aspects of the subject disclosure may include, for example, a frequency divider, comprising a plurality of delay devices arranged to receive input clocks and generate output clocks, wherein one or more of the delay devices comprises a first transconductance element configured to receive a first input and provide a first output, a second transconductance element configured to receive a second input and provide a second output, a first feedforward transconductance element that cross couples the first input and the second output, and a second feedforward transconductance element that cross couples the second input and the first output. Other embodiments are disclosed.

Method and system for boosting the speed of a ring-based frequency divider

Aspects of the subject disclosure may include, for example, a device including a phase rotator configured to receive a read clock, a flip flop configured to obtain an incoming data stream, and a controller. The controller may be configured to control the phase rotator to perform phase rotation of the read clock based on information-carrying level transitions in the incoming data stream, cause a gapped read clock and an inversion of the gapped read clock to be derived in accordance with the phase rotation, where the gapped read clock being derived via gapping operations associated with the read clock, and output clock selection signals that enable the flip flop to selectively sample the incoming data stream using the gapped read clock and the inversion, thereby facilitating a data handoff between asynchronous clock domains. Other embodiments are disclosed.

Low latency data handoff using phase rotation and clock gapping

Aspects of the subject disclosure may include, for example, an inner clock generation circuit, including: a selectable frequency divider having: a ring of tri-state inverters; a reset gate on an output of each tri-state inverter in the ring; and a reset circuit comprising one or more selectable flip-flops; and a duty-cycle limiter that generates clock signals having a 25% duty cycle from three out of four quadrature clock signals. Other embodiments are disclosed.

Apparatus and method for wideband multi-phase clock generation

Aspects of the subject disclosure may include, for example, implementing a first stage including a first number of phase rotators in parallel generating respective clock phases offset by a fixed amount; a second stage including a second number of phase rotators receiving outputs from the first number of phase rotators of the first stage, the second stage outputting a first weighted sum of respective clock phases generated by the second number of phase rotators. The subject disclosure further includes the second number of phase rotators being less than the first number of phase rotators, and a total number of bits dedicated to phase selection being split across the first stage and the second stage. Other embodiments are disclosed.

Method and apparatus for clock and data alignment that reduces power consumption

A successive approximation register based time-to-digital converter circuit with a time difference amplifier (TDA). A first TDA which applies a gain value to a time difference between a first signal edge and a first delayed signal edge to generate a first amplified time difference signal, which is feedback to the first TDA, a second TDA which applies a gain value to a time difference between a second signal edge and a second delayed signal edge to generate a second amplified time difference signal, which is feedback to the second TDA, and a finite state machine which sets another gain value, for a next step in a N step conversion until N steps are completed, in the first and the second TDAs based on a bit value from a previous step, wherein the bit value indicates, for a step, whether the first or second amplified time difference signal is ahead.

Successive approximation register based time-to-digital converter using a time difference amplifier

Described herein is a fractional phase locked loop with sigma-delta modulator (SDM) quantization noise cancellation. The fractional phase includes a digital filter configured to receive an error signal based on a comparison of a reference clock and a feedback clock, a controlled oscillator configured to generate an output clock by adjusting a frequency of the controlled oscillator based on a control signal output by the digital filter, the feedback clock being based on the output clock, a sigma-delta modulator configured to control division of the output clock to generate a divided output clock which includes a sigma-delta modulator quantization noise and a digital-to-time converter configured to receive a cancellation code from an integrator in the sigma-delta modulator and cancel the sigma-delta modulator quantization noise in the divided output clock with the cancellation code to generate the feedback clock.

Apparatus and method for Sigma-Delta modulator quantization noise cancellation

Circuits, controllers, and techniques are provided for reducing non-linearities in a phase rotator. A card include first transmit (Tx) component configured to connect to a second receive (Rx) component in a second card; a first Rx component configured to connect to a second Tx component in the second card; a single Phase-Locked Loop (PLL) circuit connected to both the first Tx component and the first Rx component; and a control circuit configured to compensate for differences between i) the first Tx component and the second Rx component, and ii) the first Rx component and the second Tx component.

An optical system includes a transmitter including transmitter circuitry configured to cause transmission of a transmitted optical signal over a fiber link on an X polarization and a Y polarization; and a receiver including receiver circuitry configured to receive a received optical signal from the fiber link on the X polarization and the Y polarization, wherein the transmitter circuitry is configured to cause State of Polarization (SOP) changes on the X polarization and the Y polarization for a test of the fiber link. The transmitter circuitry and the receiver circuitry are built-in with the transmitter and the receiver, respectively, for performance of the test.

Built-in jitter loading and state of polarization generation to characterize optical transceivers

A circuit includes a programmable frequency divider which receives a high-speed clock, f, as an input and which provides a modulated reference clock as an output; a Sigma-Delta modulator which receives a Frequency Control Word (FCW) and which is connected to the programmable frequency divider to receive the modulated reference clock as a sample clock and to control an average frequency of the modulated reference clock; and an integer-N Phase Lock Loop (PLL) which receives the modulated reference clock and outputs a clock output.

Fractional frequency synthesis by sigma-delta modulating frequency of a reference clock

A noise-shaping enhanced (NSE) gated ring oscillator (GRO)-based ADC includes a delay which delays and feedbacks an error signal to an input of the NSE GRO-based ADC. The feedback error signal provides an order of noise-shaping and the error signal is generated at the input of the NSE GRO-based ADC from an input signal, the feedback error signal, and a front-end output. A voltage-to-time converter converts the error signal to the time domain. A GRO outputs phase signals from the time domain error signal by oscillating when the error signal is high and inhibiting oscillation otherwise. A quantization device quantizes the phase signals to generate the front-end output. A quantization extraction device determines a quantization error from the quantized phase signals. A time-to-digital converter digitizes the quantization error to generate a back-end output. An output device generates a second order noise-shaped output based on the front-end and the back-end outputs.

Noise-shaping enhanced gated ring oscillator based analog-to-digital converters

An optical Digital Signal Processor (DSP) circuit includes a digital core configured to implement digital signal processing functionality and configured to operate at a plurality of baud rates including a full baud rate and a half-baud rate; and an analog interface including a Digital-to-Analog Converter (DAC) section and an Analog-to-Digital Converter (ADC) section, wherein the analog interface is connected to the digital core and is configured to operate at the full baud rate when the digital core is configured to operate at any of the plurality of baud rates.

Optical DSP operating at half-baud rate with full data rate converters

Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (F)(F/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential F/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.

Apparatus and methods for low power frequency clock generation and distribution

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Nepean, Canada

Naim Ben-Hamida