International Business Machines Corporation

Naiju K Abdul

Kerim Kalafala

Manish Verma

Hemlata Gupta

Adil Bhanji

Jeremy J Leitzen

James Douglas Warnock

Stephen Gerard Shuma

Michael H Wood

Alex Rubin

Jennifer E Basile

Rahul Rao

George Antony

Jack DiLullo

A method, a computer system, and a computer program product for scan chain wirelength optimization is provided. Embodiments of the present invention may include obtaining root nodes details from the root nodes. Embodiments of the present invention may include optimizing a connectivity of the root nodes. Embodiments of the present invention may include identifying a best start node and a best end node for each of the root nodes. Embodiments of the present invention may include optimizing child nodes in each of the root nodes. Embodiments of the present invention may include determining that a wirelength of a full tour is shorter or longer than a nearest neighbor. Embodiments of the present invention may include applying or skipping a solution.

Scan chain wirelength optimization using Q-learning based reinforcement learning

A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.

Programmable clock division methodology with in-context frequency checking

A system and method to generate a clock domain-independent abstract of a component in an integrated circuit design. The method includes performing an initial analysis of the component using an initial clock value for each clock domain type, the clock domain types including a functional clock and a test clock, executing an abstractor to obtain a reduced order model of the initial analysis as a clock domain-dependent abstract, and obtaining original constraints associated with one or more circuit elements within the component from the clock domain-dependent abstract. Generating generalized constraints is based on clock domain-dependent constraints among the original constraints, and generating the clock domain-independent abstract is based on the generalized constraints. The method also includes obtaining a physical implementation based on one or more analyses using the clock domain-independent abstract.

Clock domain-independent abstracts

A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.

Callback based constraint processing for clock domain independence

A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for a timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.

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Bengaluru, India

Naiju K Abdul