Sandisk Technologies Inc.

Naidu Prasad

Deepak Pancholi

Bhavin Odedara

Jayaprakash Naradasi

Srikanth Bojja

Srinivasa Rao Sabbineni

A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.

Self-calibrating relaxation oscillator based clock cycle

A low drop-out (LDO) voltage regulation circuit includes first and second internal current paths. The first internal current path is between the input supply voltage and ground and includes the regulator's buffer circuit. The second internal current path is between the input supply voltage and ground and includes the regulator's power transistor. The amount of current flowing through the first internal current path relative to the amount of current flowing through the second internal current path is an increasing function of a current supplied to a load connected to the output supply node. The load regulation of the LDO is improved as the DC gain will not go down at lower load currents. Further, the no load to full load response time is improved as the load pole and power MOS gate pole are actively controlled with respect to output load current. In this mechanism, as the amount of current being supplied to the load decreases, the internal current flow shifts from the first internal current path to the second internal current path and vice versa. This arrangement maintains the desired pole structure and keeps the quiescent current largely the same for all load current levels.

Controlled load regulation and improved response time of LDO with adaptive current distribution mechanism

Self-calibrating relaxation oscillator based clock source

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New Tippasandra, India

Naidu Prasad