Skyworks Solutions, Inc.

Nai-Shuo Cheng

Kevin Choi

James Phillip Young

Russ Alan Reisner

Shiaw Wen Chang

Daniel Lee Kaczman

Peter Phu Tran

Haibo Cao

Hugh J Finlay

Youngoo Yang

Bon-Seok Park

High J Finlay

Apparatus and methods for oscillation suppression are disclosed. In one embodiment, a power amplifier system includes a plurality of power amplifiers for amplifying an input radio frequency (RF) signal to generate an output RF signal. The plurality of power amplifiers include a first power amplifier, a second power amplifier, and a third power amplifier, each of which are configured to be individually switchable between an enabled state and a disabled state so as to control a power amplification of the power amplifier system. A first capacitor is electrically connected between the outputs of the first and second power amplifiers, and a second capacitor is electrically connected between the outputs of the second and third power amplifiers. The first and second capacitors are configured to allow signals generated using the first, second, and third power amplifiers to combine constructively to generate the output RF signal.

Apparatus and methods for oscillation suppression

A power amplifier having a phase shift and impedance transformation element is disclosed. The power amplifier comprises a plurality of amplification paths, a first phase shift element at an input of each amplification path and a second phase shift element at an output of each amplification path. The amplifier also comprises an impedance transformation element associated with the second phase shift element and a power combiner configured to combine an output of each amplification path into a single output.

Load variation tolerant radio frequency (RF) amplifier

An exemplary bias circuit is coupled to an amplifier. The bias circuit comprises a first bipolar transistor, a second bipolar transistor and a third bipolar transistor. The first bipolar transistor has a base connected to a first node, and the first node is connected to a reference voltage through a first resistor. The second bipolar transistor has a base connected to the first node. The third bipolar transistor has a collector connected to the first node and a base connected to an emitter of the first bipolar transistor at a second node. An emitter of the second bipolar transistor is connected to a base of a fourth bipolar transistor associated with the amplifier, and the second bipolar transistor does not have a resistor connected to the emitter of the second bipolar transistor.

Temperature-insensitive bias circuit for high-power amplifiers

According to one exemplary embodiment, a gain reduction circuit comprises a first terminal, where the first terminal is coupled to a control signal. The gain reduction circuit further comprises a second terminal, where the second terminal is coupled to an input of an amplifier, and where the amplifier is configured to operate in low-power mode and high-power mode. The gain reduction circuit further comprises a transistor coupled to the first terminal and the second terminal. The transistor can be, for example, a bipolar transistor, such as an NPN GaAs heterojunction bipolar transistor, having a base, a collector, and an emitter, where the base being is coupled the control signal, the collector is coupled to the input of the amplifier, and the emitter is coupled to ground. According to this exemplary embodiment, the transistor causes a gain of the amplifier to be reduced when the amplifier is operating in low-power mode.

Power gain reduction circuit for power amplifiers

Growing community of inventors

Simi Valley, CA, United States of America

Nai-Shuo Cheng