Via Technologies, Inc.

Via Technologyies, Inc.

Nai-Shung Chang

Chia-Hsing Yu

Shu-Hui Chen

Tsai-Sheng Chen

Ching-Fu Chuang

Chia-Hsin Chen

Jiin Lai

Chih-Hsiung Lin

Jincheng Huang

Yuangtsang Liaw

Hsuan-Yi Wang

Jang-Lih Hsieh

Hsiu-Wen Ho

Sheng-Chang Peng

Yung-Hui Chen

Wen-Ching Chang

Yuantsang Liaw

Jin-Cheng Huang

Hsiang-Chou Huang

Lie-Wen Chen

Lin Yang

Chia-Hsing Yuo

Hui-Li Chou

Lin-Hung Chang

A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.

Method for reducing power consumption of a computer system in the working state

A package substrate for a multi-package module. The package substrate comprises a substrate having a die region and at least one thermal channel region outwardly extending to an edge of the substrate from the die region. An array of bumps is arranged on the substrate except in the die and thermal channel regions, in which the interval between the bumps is narrower than the width of the thermal channel region. An electronic device with a package substrate is also disclosed.

Multi-package module and electronic device using the same

A method for dynamically increasing the data processing capability of a computer system is provided. The computer system comprises a processor, a memory and a chipset. The data processing capability of the computer system is classified into a predetermined number of performance enhancing modes. At least one performance enhancing mode transition condition is checked to determine whether to automatically raise the performance enhancing mode of the computer system. The processor is suspended from using the processor bus during the transition of the performance enhancing mode of the computer system. The performance enhancing mode of the computer system is raised by increasing a first working frequency of the processor, a second working frequency of the processor bus and a third working frequency of the memory. The data processing rate of the computer system is further increased when the performance enhancing mode of the computer system is further raised.

Method for increasing the data processing capability of a computer system

A printed circuit board (PCB) for a package substrate of a multi-package module (MPM). The PCB comprises a substrate and a heat sink thereon. The heat sink comprises a first portion under the package substrate of the MPM. The heat sink further comprises a second portion adjacent to the first portion, comprising at least one fin.

Printed circuit board for thermal dissipation and electronic device using the same

The graphics display architecture provided by the present invention comprises an AGP slot, a PCIE slot, and a control chip set. The control chip set comprises a plurality of multi-defined pins, which are electrically coupled to the first pins of the AGP slot and the second pins of the PCIE slot simultaneously. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with AGP interface specification, the multi-defined pins serve to send/receive the signal complied with AGP interface specification. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with the Gfx interface, the multi-defined pins serve to send/receive the signal complied with the Gfx interface. When the second graphics adapter is plugged in the PCIE slot, the multi-defined pins serve to send/receive the signal complied wit the PCIE interface specification.

Graphics display architecture and control chip set thereof

A structure and a method for an extended bus and a bridge in the extended bus are disclosed. The structure of the extended bus has a first accelerated graphics port bus, a first bridge, a second accelerated graphics port bus and a first extended bus. The first bridge performs a compatible mutual conversion of the signal and data between the first accelerated graphics port bus and the first extended bus or the second accelerated graphics port bus, so that the first accelerated graphics port bus is extended for use. The invention extends and expands the current available high-speed and wide-bandwidth accelerated graphics port bus to obtain one or more extended buses. The data path through the south bridge chip is thus avoided. Furthermore, more expansion slots are provided to the system, and the flexibility of expanding the computer system is increased.

Structure and method for extended bus and bridge in the extended bus

A method of operating a chipset for saving power consumption is provided. Basic operating units, control units and input/output ports are used to simulate the operation inside the chipset. Any idling operating units are temporarily shut down, only to be activated again on demand. Ultimately, less power consumption is used and less heat is generated by the chipset.

Method for saving chipset power consumption

A wire bonding BGA package. On a conductive metal layer of a substrate used for carrying a die, a power ring for providing an operating voltage to a core circuit of the die is disposed in the inner side of a power ring for providing an operating voltage to an input/output circuit of the die. When the die is packaged by flip chip packaging instead of wire bonding packaging, the power ballout assignment of the BGA package is unchanged and is suitable for matching with an original circuit board used for the flip chip BGA package. In addition, the present invention provides a flip chip BGA package. When the die is packaged by wire bonding packaging instead of flip chip packaging, the power ballout assignment of the BGA package is unchanged and is suitable for matching with an original circuit board used for the wire bonding BGA package.

BGA package with same power ballout assignment for wire bonding packaging and flip chip packaging

An I/O pad has a data transmitting circuit, a data monitoring control circuit, and a control selection circuit. The control selection circuit controls the data transmitting circuit. When it is enabled, data in the data transmitting circuit are exported to a receiving circuit. When it is disabled, data exportation stops. The data monitoring circuit receives signals of the data transmission circuit and export signals to the control selection circuit. The data monitoring circuit judges whether the data transmission is under a stable condition. If it is not, an unstable signal is exported to a first input end of the control selection circuit. A second input end of the control selection circuit receives an output enabling signal. When the data transmission is stable and the output enabling signal indicates a disable status, the control selection circuit disables the data transmitting circuit. Otherwise, the control selection circuit enables the data transmitting circuit.

Operation method of input/output pad with monitoring ability

A motherboard with reduced power consumption is disclosed. The motherboard has a memory module slot, a DDR termination array, and a control chip. The DDR termination array couples to the memory module slot and provides a termination resistor that has one terminal coupled to a voltage source. The control chip provides a control signal. When the motherboard enters a power saving mode or before the memory module being inserted in the memory module slot, the control signal gives an indication to the DDR termination array for cutting off the connection between the termination resistor and the memory module slot. A switch and several termination resistors may substitute the DDR termination array as requirements. The control chip provides the control signal to open the switch and therefore cuts off the connections between termination resistors and the voltage source to achieve the power-conserving purpose.

Motherboard with reduced power consumption

A memory control chip, control method and control circuit. Instead of accessing a plurality of memory modules in a memory bank by referencing the same clocking signal, each memory module references a clocking signal having the same frequency but a slightly different preset phase so that the data within each memory module is accessed at a slightly different time. Ultimately, simultaneous switch output noise is greatly reduced and fewer power/ground pins are required in a package.

Memory control chip, control method and control circuit

An apparatus and a method for supporting multi-processors and a motherboard using the same are provided. The apparatus receives the pins Zand AKof the Socket-central processing unit to determine which type the Socket-central processing unit is. According to the suspend status input signal transmitted from the south bridge of the motherboard, the determined result is latched, and some appropriate circuits are coupled to the Socket-central processing unit via a switch circuit. Meanwhile, the suspend status input signal is delayed and used to cut off the connection between the Socket-central processing unit and the apparatus. The delayed suspend status input signal is further delayed and then sent to an ATX power supply to activate the whole system.

Apparatus and method for supporting multi-processors and motherboard of the same

A suspend-to-RAM controlling circuit includes a RAM (random access memory) controller, a logic circuit and at least one RAM module. The RAM controller has a controlling pin connected to the logic circuit. Each of the RAM modules has a first enable pin and a second enable pin connected to output pins of the logic circuit. The RAM module is driven to the STR (suspend-to-RAM) state after receiving an STR signal from the logic circuit. Therefore, the RAM controller can provide STR signals to a plurality of RAM modules by only one controlling pin in incorporation with the logic circuit.

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Taipei Hsien, Taiwan

Nai-Shung Chang