Macronix International Co., Ltd.

Nai-Ping Kuo

Chun-Hsiung Hung

Kuen-Long Chang

Ken-Hui Chen

Han-Sung Chen

Su-Chueh Lo

Ming-Chih Hsieh

Yu-Chen Wang

Chien-Hsin Liu

Chin-Hung Chang

Ho-Chun Liou

Chia-Feng Cheng

Hsin-Yi Ho

Ting-Yu Liu

Chuan-Ying Yu

Shih-Chou Juan

Wen-Pin Tsai

Shuo-Nan Hung

Wen-Yi Hsieh

Hsiang-Pang Li

Wen-Chiao Ho

Wei-Chieh Huang

Yu-Ming Chang

Hung-Sheng Chang

Yi-Chun Liu

Yung Feng Lin

Chang-Ting Chen

Li-Chun Huang

Ching-Chung Lin

Chao-Hsin Lin

Ching-chung Lin

Chun Hsiung Hung

Shih-Chang Huang

Yu-Meng Chaung

Kuan-Chieh Wang

Kuo-Yu Liao

Yuchih Yeh

Yi Chun Liu

Tu-Shun Chen

Shih Chou Juan

Shunli Cheng

Hsieh-Ming Chih

Gin-Liang Chen

Jian-Shing Liu

Cai-Yun Wu

Min-Hsiung Meng

Wen-Ming Hsu

Gin-Laing Chen

Jianshing Liu

Chin Chu Chung

Shihchou Juan

Yen-Hsiang Chen

Jia-Xing Lin

A memory system that is based on 3D NAND flash memory of a high capacity and/or capable of high performance is provided, which includes memory planes, each including a plane core and a specific set of resources. For each memory plane of the plurality of memory planes, the technology provides (i) a corresponding plane busy (PRDY) signal indicating a busy or a ready state of the specific set of recourses of the corresponding memory plane, and (ii) a corresponding plane in operation (PIO #) signal indicating an in operation or idle state of resources used by the plane core of the corresponding memory plane. Issuance of memory commands by a controller and execution of memory commands for a memory plane of the plurality of memory planes is selectively allowed or denied, based on status of one or more of the plurality of PRDY signals and the plurality of PIO # signals.

Memory system having planes with multibit status

A memory device and a management method thereof are provided. The memory device includes a controller and at least one memory channel. The memory channel includes at least one memory chip. The at least one memory chip is commonly coupled to the controller through an interrupt signal wire. The at least one memory chip generates at least one local interrupt signal and performs a logic operation on the at least one local interrupt signal to generate a common interrupt signal. The interrupt signal wire is configured to transmit the common interrupt signal to the controller.

Memory device and management method thereof

A solid state disk, a data transmitting method and an intermediary controller thereof are provided. The solid state disk includes at least two flash memories, a SSD controller and an intermediary controller. The intermediary controller is connected between the flash memories and the SSD controller. The intermediary controller includes at least two flash interfaces, a customized interface and a data buffering unit. The flash interfaces are connected to the flash memories. The customized interface is connected to the SSD controller. The intermediary controller has a first clock domain and a second clock domain. The first clock domain is used for transmitting data from the flash memories to the data buffering unit. The second clock domain is used for transmitting data from the data buffering unit to the SSD controller. A frequency of the second clock domain is higher than a frequency of the first clock domain.

Solid state disk, data transmitting method and intermediary controller to support reduced SSD controller pad count

A method of operating a memory comprising a plurality of memory planes is disclosed. Each memory plane includes at least one corresponding memory array. The method includes, for each memory plane of the plurality of memory planes, generating (i) a corresponding plane ready (PRDY) signal indicating a busy or a ready state of the corresponding memory plane, and (ii) a corresponding plane array ready (PARDY) signal indicating a busy or a ready state of the corresponding memory array of the corresponding memory plane, such that a plurality of PRDY signals and a plurality of PARDY signals are generated corresponding to the plurality of memory planes. Execution of a memory command for a memory plane of the plurality of memory planes is selectively allowed or denied, based on status of one or more of the plurality of PRDY signals and the plurality of PARDY signals.

Memory supporting multiple types of operations

A method for sensing temperature in memory die, memory die and memory with temperature sensing function are provides. The memory die includes at least one temperature monitoring for outputting a temperature status in the memory die; a temperature sensor, arranged in the memory die for sensing an operation temperature in the memory die; and a control logic unit, coupled to the temperature sensor for receiving the operation temperature and coupled to the temperature monitoring pin. The control logic unit compares the operation temperature and a threshold value received from outside of the memory die to generate a comparison result, and outputs the temperature status through the temperature monitoring according to the comparison result.

Method for sensing temperature in memory die, memory die and memory with temperature sensing function

A memory device and a method for reducing read disturb errors of the memory device are provided. The memory device includes a plurality of memory cells arranged in series and organized into a plurality of blocks, a plurality of word lines respectively coupled to corresponding memory cells, and a controller coupled to the word lines for performing page read operations on the pages in respective blocks through corresponding word lines, in which each of the blocks comprises a plurality of pages of two or more types. The controller accumulates a page read count of the pages of each type in respective blocks, and arranges data to be stored according to the page read count and a latency factor corresponding to the pages of each type in each of the blocks.

Memory device and method for managing read counts of memory device

A method for an erase operation on a nonvolatile memory array with low-latency erase suspend is described. The nonvolatile memory array includes a plurality of blocks of memory cells, each block including a plurality of sectors of memory cells. The method includes, in response to an erase command identifying a block in the plurality of blocks in the array, erasing the plurality of sectors in the identified block, and determining whether there are over-erased cells in each sector. The method includes recording the over-erased cells for the sector. The method also includes responsive to suspend before a soft program pulse for the sector, applying a correction pulse to the recorded cells.

Low latency memory erase suspend operation

A memory system includes a first flash memory, a second flash memory and a controller. The first flash memory includes a memory array divided into a plurality of pages. The controller is coupled to the first flash memory and the second flash memory and configured to: control the second flash memory to record an address of a particular page in the first flash memory before programming the particular page; and control the second flash memory to record a program status of the particular page after the particular page has been programed.

Memory system and operating method thereof

A method for writing data into a persistent storage device includes grouping a plurality of data entries stored in a temporary storage device to form a data unit, such that the data unit has a size equal to an integer multiple of a size of an access unit of the persistent storage device. The method further includes writing the data unit into the persistent storage device.

Method, apparatus, and storage medium for writing data into persistent storage device

A memory device includes a first storage unit storing an address mapping table, and a control unit coupled to the first storage unit and including a second storage unit storing a risky mapping table and a cached mapping table. The control unit is configured to: write data into the first storage unit; update mapping information associated with the data in the risky mapping table; and store mapping information in the cached mapping table into the address mapping table.

Memory device including risky mapping table and controlling method thereof

A method for reading data from memory cells of a target word line in a semiconductor memory includes determining a disturbance status of the target word line. The disturbance status reflects a disturbance of a neighboring word line on the memory cells of the target word line. The method further includes determining a read voltage for the target word line according to the disturbance status of the target word line and applying the read voltage to the memory cells of the target word line.

Method and device for reading a memory

A memory device includes a memory controller and a non-volatile memory communicatively coupled to the memory controller and storing a mapping table and a journal table. The memory controller is configured to write data and a logical address of the data into the non-volatile memory, load mapping information related to the logical address of the data from the mapping table of the non-volatile memory into a mapping cache of the memory controller, update the mapping cache with an updated mapping relationship between the logical address of the data and a physical address of the data, and perform a journaling operation to write the updated mapping relationship into the journal table.

Memory device and operating method of same

A method, an electronic device and a controller for recovering an array of memory cells are provided. The method comprises the following steps. Whether a recovery control signal is received or not is determined. A retention checking procedure is executed for identifying whether a threshold voltage distribution of at least one bit of the memory cells in high threshold state is shifted or not, if the recovery control signal is received. A retention writing procedure is executed on the memory cells, if the memory cells in high threshold state do not pass the retention checking procedure.

Method, electronic device and controller for recovering array of memory cells

A method of operating a memory storing data sets, and ECCs for the data sets is provided. The method includes when writing new data in a data set, computing and storing an ECC, if a number of addressable segments storing the new data and data previously programmed in the data set includes at least a predetermined number of addressable segments. The method includes storing indications for whether to enable or disable use of the ECCs, using the ECC and a first additional ECC bit derived from the ECC. The method includes reading from a data set an extended ECC including an ECC and a first additional ECC bit derived from the ECC, and enabling or disabling use of the ECC according to the indications stored for the data set. The method includes enabling use of ECCs for blank data sets, using the indications and a second additional ECC bit.

ECC method for flash memory

An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state. Retention check logic executes to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.

Retention logic for non-volatile memory

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Hsinchu, Taiwan

Nai-Ping Kuo