Anaglobe Technology, Inc.

Nai-Chen Chen

Chun-Yu Lin

Yu-Tsang Hsieh

Po-Hung Lin

Vincent Weihao Hsiao

A method for parasitic-aware capacitor sizing and layout generation is proposed, which is executed by a computer, the method comprising using the computer to perform the following: creating a capacitor sizing and parasitic matching sequence to represent a unit capacitor size, routing topology and routing patterns of a plural of nets in a capacitor network. Next, a shielding assignment is performed to create a number of shielding portions of each net in the plural of nets. Then, a fitness evaluation of configurations of the capacitor sizing and parasitic matching sequence is performed. A shielding net routing is performed to compensate unmatched parasitic capacitance of the configurations of the capacitor sizing and parasitic matching sequence.

Growing community of inventors

Tainan, Taiwan

Nai-Chen Chen