Freescale Semiconductor,inc.

Nageswara Rao Bonda

Zhiwei Gong

Wei Gao

Dehong Ye

Jinsheng Wang

A method and apparatus are described for fabricating a low-pin-count chip package () including a die pad () for receiving an integrated circuit device and a plurality of connection leads () having recessed lead ends () at the outer peripheral region of each contact lead. After forming the package body () over the integrated circuit device, unplated portions () of the exposed bottom surface of the selectively plated lead frame are partially etched to form recessed lead ends () at the outer peripheral region of each contact lead, and the recessed lead ends are subsequently re-plated () to provide wettable recessed lead ends at the outer peripheral region of each contact lead.

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Chandler, AZ, United States of America

Nageswara Rao Bonda