Intel Corporation

Sandisk Technologies Inc.

Rigetti & Co, LLC

Other

Altera Corporation

Western Digital Technologies, Inc.

Nagesh K Vodrahalli

Biswajit Sur

Achintya K Bhowmik

Ut Tran

Ruolin Li

Hamid Eslampour

William Wong

Hai-Feng Liu

Gennady Farber

Chad Tyler Rigetti

Suresh Ramalingam

Mehrnoosh Vahidpour

Rama Shukla

Andrew Joseph Bestwick

James Russell Renzas

Jayss Daniel Marshall

William Austin O'Brien, Iv

Chih-Yang Li

Venkatesan Murali

Ravi V Mahajan

Shrikar Bhagath

Connie C Liu

Thomas Workman

Mun Leong Loke

Michael J Costello

Kenji Takahashi

Jesper Arentoft Jayaswal

Takaharu Fujiyama

Toshiki Hirano

Jon M Long

Michael P Brownell

Vipin Ayanoor-Vitikkate

Duane Cook

Brian A Kaiser

Richard Michael Ramirez

Jaiom S Sambyal

James G Maveery

Chih Yang Li

Jesper Jayaswal-Arentoft

Srinivasan Sivaram

Jesper Jayaswal-Arentoff

A processing core includes a multi-core processor integrated directly onto a high bandwidth, high-capacity non-volatile memory. The processor may for example be a large graphics processing unit (GPU) or artificial intelligence (AI) processor. The non-volatile memory may comprise a CBA (CMOS bonded to array) memory tile having a single large NAND memory tile coupled together with a CMOS logic circuit tile. The integrated processor and CBA memory tile may be affixed to an interposer. The processing core may further include stacks of high bandwidth memory (HBM) semiconductor dies affixed to the interposer around one or more sides of the processor and CBA memory tile.

Processing core including integrated high capacity high bandwidth storage memory

In a general aspect, an integrated quantum circuit includes a first substrate and a second substrate. The first substrate includes a first surface and a recess formed in the first substrate along the first surface. The recess has a recess surface and is configured to enclose a quantum circuit element. The first substrate includes a first electrically-conductive layer disposed on the first surface and covering at least a portion of the recess surface. The first electrically-conductive layer includes a first superconducting material. The second substrate includes a second surface and a quantum circuit element. The second substrate includes a second electrically-conductive layer on the second surface that includes a second superconducting material. The first substrate is adjacent the second substrate to enclose the quantum circuit device within the recess. The first electrically-conductive layer of the first substrate is electrically-coupled to the second electrically-coupled layer of the second substrate.

Microwave integrated quantum circuits with cap wafers and their methods of manufacture

A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. Once bonded, respective inactive surfaces of the wafers may be thinned and then the die pairs diced from the wafers to form a completed memory module. When the wafers are bonded face to face, they compensate each other, mechanically resulting in the die pair having a minimum warpage.

Memory scaling semiconductor device

A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level, mechanically resulting in the die pair having a minimum warpage. An electronic component may be bonded to an exposed surface of one of the semiconductor dies.

A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. The semiconductor device may further include a CMOS logic circuit as part of the pair of semiconductor dies or in its own semiconductor die mounted to the pair of semiconductor dies.

In a general aspect, an integrated microwave circuit is disclosed for processing quantum information. The integrated microwave circuit includes a substrate having a first surface and a second surface opposite the first surface. The substrate is formed of a silicon oxide material having a loss tangent no greater than 1&#xd7;10at cryogenic temperatures at or below 120 K. The integrated microwave circuit also includes qubit circuitry disposed on the first surface that includes a Josephson junction. A ground plane is disposed on the first surface or the second surface. In some variations, the silicon oxide material is fused silica. In other variations, the silicon oxide material is crystalline quartz.

Substrate materials for quantum processors

A semiconductor device is disclosed including semiconductor dies stacked with an offset in two orthogonal directions. TSVs may then be formed connecting corresponding die bond pads on respective dies in the stack. By offsetting the dies in two orthogonal directions, the overall stepped offset, and consequently the size of the unused keep-out area of the stack, is reduced.

TSV semiconductor device including two-dimensional shift

Techniques for electrically testing a flip-chip assembly during its manufacture include a flip-chip assembly having an integrated circuit (IC) die and an IC package substrate. The IC package substrate is placed on a substrate part holder that includes test sockets and heating elements. The IC die is then placed on the placed IC package substrate. The placed IC die and IC package substrate are aligned such that conductive contacts are formed from conductive bumps and pads deposited on the surface of the IC die and IC package substrate. While the bumps and pads are in conductive contact, but prior to attachment, the flip-chip assembly is electrically tested. If the flip-chip assembly passes electrical testing, the conductive contacts may be attached by the heating elements on the substrate part holder, such as in a solder reflow process when the bumps are made from solder.

Method and apparatus for testing a flip-chip assembly during manufacture

Techniques for electrically testing an integrated circuit (IC) die with a partially completed and validated module (module) include providing an IC die to be tested on an IC package substrate of a validated test module, the positioned IC die and the module forming a multi-die flip-chip test assembly, and without attaching the interconnection bumps of the IC die to the package pads of the module, electrically testing the multi-die flip-chip test assembly. The method may further involve, responsive to the multi-die flip-chip test assembly passing electrical testing positioning the IC die on a production IC package substrate and attaching the IC die to the production IC package substrate. Corresponding apparatus and systems can also be used to perform the technique.

Method and apparatus for testing integrated circuit die with a partially completed and validated module

A method of fabricating an electronic assembly includes fabricating first and second interconnects. The first interconnect is adapted to interconnect a first die to a substrate. The second interconnect is adapted to interconnect the first die to a second die. The method further includes assembling the first die, the second die, and the substrate together such that the first die is disposed above the substrate, and the second die is disposed below the first die.

Electronic assembly apparatus and associated methods

The present invention involves a method of providing an integrated circuit package having a substrate with a vent opening. The integrated circuit package includes a substrate having an opening and an integrated circuit mounted to the substrate. An underfill material is dispensed between the substrate and the integrated circuit.

Process for assembling an integrated circuit package having a substrate vent hole

Growing community of inventors

Cupertino, CA, United States of America

Nagesh K Vodrahalli