Renesas Technology Corp.

Renesas Electronics Corporation

Hitachi Ulsi Systems Co., Ltd.

Hitachi-johnson Controls Air Conditioning, Inc.

Nagatoshi Ooki

Akihiro Shimizu

Yusuke Nonaka

Katsuhiko Ichinose

Satoshi Sakai

Naoki Yamamoto

Kenji Matsumura

Takeshi Endo

Mamoru Houfuku

Shuuhei Tada

Kiyota Hachimine

An air conditioner that includes a heat exchanger including: heat-transfer pipes extending in a horizontal direction and spaced apart at predetermined intervals in a vertical direction and configured to allow a thermal medium to flow therein. A part of the heat transfer pipes are used for at least one inflow path into which the thermal medium flows from the outside of the heat exchanger and the other part of the heat transfer pipes are used for at least one outflow path from which the thermal medium flows out to the outside. At least one connection pipe through which an outlet side of one of the at least one inflow path communicates with an inlet side of one of the at least one outflow path.

Air conditioner

A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.

P-channel transistor having an increased channel mobility due to a compressive stress-inducing gate electrode

Semiconductor device and a method of manufacturing the same

Semiconductor device including a film for applying stress to a channel formation region to increase current flow

Semiconductor device including a nitride containing film to generate stress for improving current driving capacity of a field effect transistor

A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.

Structure and method of applying localized stresses to the channels of PFET and NFET transistors for improved performance

CMOS transistors using gate electrodes to increase channel mobilities by inducing localized channel stress

Semiconductor device including stress inducing films formed over n-channel and p-channel field effect transistors and a method of manufacturing the same

A method of manufacturing a semiconductor device having an n-type FET and p-type FET, each formed over a semiconductor substrate, calls for (a) forming, over the n-type FET and p-type FET, a first insulating film, for generating a tensile stress in the channel formation region of the n-type FET, to cover gate electrodes of the FETs, while covering, with an insulating film, a semiconductor region between the gate electrode of the p-type FET and an element isolation region of the semiconductor substrate; (b) selectively removing the first insulating film from the upper surface of the p-type FET by etching; (c) forming, over the n-type and p-type FETs, a second insulating film, for generating a compressive stress in the channel formation region of the p-type FET, to cover gate electrodes of the FETs; and (d) selectively removing the second insulating film from the upper surface of the n-type FET.

Growing community of inventors

Shimizu, Japan

Nagatoshi Ooki